Abstract: A multiple finger off chip driver (OCD) has a single level translator for each of a plurality of PFET fingers and NFET fingers which allow the impedance of the OCD to be varied to match the impedance of a driven load. A plurality of PFET and NFET finger selection devices are used to select various combinations of output FETS and ballast resistor finger combinations to drive an output signal at a desired impedance level. The ballast resistors are scaled in ohmic value to the size of the output finger it is connected to. In this configuration, a constant ratio of FET impedance to ballast resistance is maintained in each drive stage (finger). By selecting various combinations of fingers various driver impedances can be selected.

Abstract: The invention provides a trench storage structure that includes a substrate having a trench, a capacitor conductor in the lower part of the trench, a conductive node strap in the trench adjacent the capacitor conductor, a trench top oxide above the capacitor conductor, and a conductive buried strap in the substrate adjacent the trench top oxide. The trench top oxide includes a doped trench top oxide layer above the conductive strap, and an undoped trench top oxide layer above the doped trench top oxide layer.

Abstract: A trench capacitor memory cell structure is provided with includes a vertical collar region that suppresses current leakage of an adjacent vertical parasitic transistor that exists between the vertical MOSFET and the underlying trench capacitor. The vertical collar isolation, which has a vertical length of about 0.50 &mgr;m or less, includes a first portion that is present partially outside the trench and a second portion that is present inside the trench. The first portion of the collar oxide is thicker than said second portion oxide thereby reducing parasitic current leakage.

Abstract: An anti-fuse system composed of a multiplicity of anti-fuse circuits (24, 26, 28, N) connected across a voltage source (10) by a pair of conductors (16, 18). Each anti-fuse circuit comprising an anti-fuse (30) connected in series with a blow or control transistor (36) and a control circuit (44) for monitoring the status of the anti-fuse (30) at a voltage node (48) located between the anti-fuse (30) and blow transistor (36). When operating in a blow cycle, control circuit (44) provides an “on” signal to the gate (38) of blow transistor (36) only when a select signal is received at an input (46) of control circuit (44) and if anti-fuse (30) has not been blown. Therefore, after the anti-fuse (30) is blown, control circuit (44) turns off blow transistor (36) thereby providing a constant power source voltage across each anti-fuse circuit (24, 26, 28, N) regardless of the number of parallel anti-fuses which have been blown.

Abstract: Access control to protected resources in a multiprocessor system is implemented without additional use of the processor bus. A bridge interconnects each processor with shared resources. The bridge has a semaphore corresponding to each protected resource indicating if the corresponding resource is available. The bridge halts a processor requesting access to any resource having a corresponding semaphore indicating the requested resource is not available.

Abstract: A method and structure for a dynamic random access memory device comprising a storage trench, a storage conductor within the storage trench, a lip strap connected to the storage conductor, and a control device electrically connected to the storage conductor through the lip strap. The trench contains a corner adjacent the control device and the lip strap and has a conductor surrounding the corner. The control device has a control device conductive region adjacent the trench and the lip strap and has a conductor extending along a side of the trench and along a portion of the control device conductive region. In addition, the device can have a collar insulator along a top portion of the trench, wherein the lip strap includes a conductor extending from a top of the collar to a top of the trench. The lip strap can also extend along a surface of the device adjacent the trench and perpendicular to the trench.

Abstract: A charge pump generator system and method is provided in which one or more charge pumps are operated at multiple charging rates depending upon the level reached by a voltage supply. The system includes a limiter which provides a control signal based upon the level of the voltage supply. The control signal selects the frequency of a multiple frequency oscillator coupled thereto. The selected frequency determines the charge transfer rate of a charge pump used to maintain the voltage supply.

Abstract: A method for forming a semiconductor device includes providing a semiconductor body having source and drain regions therein and a gate electrode on a portion of a surface of such body between the source and drain regions. A dielectric layer is provided on the surface of the semiconductor body over the source and drain regions. A dielectric material is formed over the dielectric layer and over the gate electrode. An inorganic, dielectric layer is formed over the semiconductor body dielectric material. The inorganic, dielectric layer is patterned into a mask to expose selected portions of the dielectric material, such portions being over the source and drain regions. An etch is brought into contact with the mask. The etch removes the exposed underlying portions of the dielectric material and exposed underling portions of the dielectric layer to thereby expose the portions of the source and drain regions.

Abstract: A dynamic random access memory is formed in a silicon chip in arrays of clusters, each of four cells in a single active area. Each active area is cross-shaped with vertical trenches at the four ends of the two crossbars. The central region of the active area where the two crossbars intersect serves as the common base region of the four transistors of the cluster. The top of the base region serves as a common drain for the four transistors and each transistor has a separate channel along the wall of its associated vertical trench that provides its storage capacitor. Each cluster includes a common bit line and four separate word-line contacts.

Abstract: A "porous barrier" is formed without formation of a discrete barrier layer by enriching grain boundaries of a body of polysilicon with nitrogen to inhibit thermal mobility of silicon species therealong. In a polycide gate/interconnect structure, the reduced mobility of silicon suppresses agglomeration of silicon in a metal silicide layer formed thereon. Since silicon agglomeration is a precursor of a polycide inversion phenomenon, polycide inversion which can pierce an underlying oxide and cause device failure is effectively avoided.

Abstract: A method for extracting n bits out of a data word stored in two concatenated registers each having a bit size of n bits starting with the m-th bit of the data register, m being smaller than n, comprises the following steps: The m significant bits of the first register are replaced with the m significant bits of the second register. Then, the result is stored in a register. Finally, the content of this register is rotated by m bits.