Abstract: In one embodiment, a semiconductor package includes a vertical semiconductor chip having a first major surface on one side of the vertical semiconductor chip and a second major surface on an opposite side of the vertical semiconductor chip. The first major surface includes a first contact region and the second major surface includes a second contact region. The vertical semiconductor chip is configured to regulate flow of current from the first contact region to the second contact region along a current flow direction. A back side conductor is disposed at the second contact region of the second major surface. The semiconductor package further includes a first encapsulant in which the vertical semiconductor chip and the back side conductor are disposed.

Abstract: Embodiments relate to integrated circuits with protection. In one embodiment the protection is coupled between a first circuit provided to control a low power mode of the integrated circuit and a supply voltage. The protection comprises in an embodiment a transistor being one of a depletion transistor or a junction field effect transistor.

Abstract: In accordance with an embodiment, a frequency doubling circuit includes a differential transistor pair coupled to an input port of the frequency doubling circuit, a first differential cascode stage having an input coupled to an output of the differential transistor pair, a plurality of first impedance elements coupled between the output of the differential transistor pair and the input of the first differential cascode stage, and an output combining network coupled between the first differential cascode stage and an output port of the frequency doubling circuit.

Abstract: An Error signal handling comprises a circuitry configured to receive an error signal from an external device indicating an error condition in the external device. The circuitry is further configured to receive a recovery signal indicating a mitigation of the error condition in the external device or indicating that a mitigation of the error condition in the external device is possible. Furthermore, the circuitry is further configured to output an error condition signal based on the error signal in response to a reception of the error signal if within a given delay time from the reception of the error signal, the circuitry does not receive the recovery signal and otherwise to omit outputting the error condition signal.

Abstract: One or more embodiments relate to a semiconductor structure, comprising: a barrier layer overlying a workpiece surface; a seed layer overlying the barrier layer; an inhibitor layer overlying said seed layer, the inhibitor layer having a opening exposing a portion of the seed layer, and a fill layer overlying the exposed portion of the seed layer.

Abstract: A semiconductor device includes a semiconductor body including a first surface. The semiconductor device further includes a continuous silicate glass structure over the first surface. A first part of the continuous glass structure over an active area of the semiconductor body includes a first composition of dopants that differs from a second composition of dopants in a second part of the continuous glass structure over an area of the semiconductor body outside of the active area.

Abstract: A lithium battery includes a cathode, an anode including a component made of silicon, a separator element disposed between the cathode and the anode, an electrolyte, and a substrate. The anode is disposed over the substrate or the anode is integrally formed with the substrate.

Abstract: According to one embodiment of a capacitor module, the capacitor module includes a substrate having a metallization on a first side of the substrate, a plurality of connectors electrically coupled to the metallization and a plurality of capacitors disposed on the metallization. The plurality of capacitors includes a first set of capacitors electrically connected in parallel between a first set of the connectors and a second set of the connectors. The capacitor module further includes a housing enclosing the plurality of capacitors within the capacitor module.

Abstract: A method for manufacturing a plurality of chips comprises the step of providing a wafer comprising a plurality of chip areas separated by one or more dicing lines, wherein the chip areas are arranged on a first main surface, the step of providing a laser absorption layer on a second main surface opposite to the first main surface and the step of providing a backside metal stack on the laser absorption layer. After that a laser light is applied to the laser absorption layer along the dicing lines before the chips are singulated along the dicing lines by using stealth dicing.

Abstract: A charge balancing circuit and an energy storage arrangement with a charge balancing circuit are disclosed.

Abstract: An embodiment of the invention relates to a local area sensor network including a central unit configured to receive a resource allocation request from a priority network sensor in a reserved timeslot and in response to designate a shared timeslot allocation. The priority network sensor transmits a resource allocation request in a reserved timeslot, and the sensor transmits data in the allocated shared timeslot. A sensor network can be formed with multiple gateways that each communicate over wired and wireless portions of the network. The central unit communicates with the gateways over the wired portion of the network. Wireless nodes communicate wirelessly with the gateways. The central unit receives a plurality of link quality indicators from the gateways for respective wireless paths to the wireless sensors, and selects a gateway for relaying a message from the central unit to a wireless sensor based on the link quality indicators.

Abstract: Embodiments relate to system and methods including a plurality of nonvolatile memory elements wherein sets of least two nonvolatile memory elements each share one select element for selecting one of the nonvolatile memory elements of a particular one of the sets of nonvolatile memory elements for a read operation or a program operation.

Abstract: The method comprises providing a carrier, providing a plurality of semiconductor chips, the semiconductor chips each comprising a first main face and a second main face opposite to the first main face and side faces connecting the first and second main faces, placing the semiconductor chips on the carrier with the second main faces facing the carrier, and applying an encapsulation material to the side faces of the semiconductor chips.

Abstract: A method for manufacturing a plurality of nanowires, the method including: providing a carrier comprising an exposed surface of a material to be processed and applying a plasma treatment on the exposed surface of the material to be processed to thereby form a plurality of nanowires from the material to be processed during the plasma treatment.

Abstract: A sensor package is disclosed. One embodiment provides a sensor device having a carrier, a semiconductor sensor mounted on the carrier and an active surface. Contact elements are electrically connecting the carrier with the semiconductor sensor. A protective layer made of an inorganic material covers at least the active surface and the contact elements.

Abstract: A method of receiving a data transmission includes detecting a first switching of a transmission signal to a first signal value, starting a duration measurement of a first time interval that begins with detecting the first switching of the transmission signal, detecting a second switching of the transmission signal to a second signal value, stopping the measurement of the first time interval duration and starting a second duration measurement of a second time interval, detecting a third switching of the transmission signal to the first signal value or to a third signal value, stopping the second measurement in response to detecting the third switching, determining a relation of the first and second time interval durations from the first and second measurements, and determining a data value of the transmission signal based on the determined relation.

Abstract: A chip arrangement is provided, the chip arrangement, including a carrier; a first chip electrically connected to the carrier; a ceramic layer disposed over the carrier; and a second chip disposed over the ceramic layer; wherein the ceramic layer has a porosity in the range from about 3% to about 70%.

Abstract: A chip arrangement is provided, the chip arrangement, including: a carrier; at least one chip including at least one contact pad disposed over the carrier; an encapsulation material at least partially surrounding the at least one chip and the carrier; and at least one low temperature co-fired ceramic sheet disposed over a side of the carrier.

Abstract: A MEMS device and a method to manufacture a MEMS device are disclosed. An embodiment includes forming trenches in a first main surface of a substrate, forming conductive fingers by forming a conductive material in the trenches and forming an opening from a second main surface of the substrate thereby exposing the conductive fingers, the second main surface opposite the first main surface.

Abstract: A chip arrangement is provided, the chip arrangement, including a carrier; at least one chip electrically connected to a carrier top side; an encapsulation material at least partially surrounding the at least one chip and the carrier top side, wherein the encapsulation material is formed on one or more lateral sides of the carrier; and a ceramic material disposed on a carrier bottom side, and on at least one side of the encapsulation material.