Abstract: A laminate is formed from a carrier layer and an electrically conductive layer. In one section, the conductive layer is formed into an antenna structure. The laminate is formed by placing a mask onto a packaging film and vapor-depositing aluminum onto the packaging film and the mask. After removal of the mask, only a desired antenna structure remains on a section of the packaging film. Then a microchip, is adhesively bonded to the packaging film and conductively connected to an end of the antenna structure, so that data can be written in or read out without contact in a wireless transponder system.

Abstract: The present invention refers to a method for writing data into a memory cell of a conductive bridging random access memory and to a memory circuit comprising memory cells with programmable metallization cells, particularly a CBRAM memory circuit. The embodiments of the prevent invention provide a method and a memory circuit for holding adjacently arranged bit lines at writing voltages during a writing operation of a selected memory cell to reduce voltage crosstalk.

Abstract: A bipolar transistor and method of making a bipolar transistor is disclosed. In one embodiment, the bipolar transistor includes a polysilicon layer into which impurity atoms are inserted, thereby reducing the layer resistance.

Abstract: The invention relates to a clock signal synchronizing method, and to a clock signal synchronizing device (101) to be used with the synchronization of clock signals (CLK, DQS), comprising: a delay means (102) with a variably controllable delay time (tvar), in which a clock signal (CLK) or a signal obtained therefrom is input, is loaded with the variably controllable delay time (tvar), and is output as delayed clock signal, a phase comparator (104) for comparing the phase of the clock signal (CLK) or of the signal obtained therefrom with the phase of the delayed clock signal or of a signal obtained therefrom (DCLK, FB), characterized in that additionally a means (401, 116) is provided for activating and/or deactivating said clock signal synchronizing device (101) as a function of control signals (RD) evaluated by an evaluating means (402).

Abstract: A semiconductor is disclosed. In one embodiment, the semiconductor includes a semiconductor substrate having an active area region, a covering configured to protect the active area region, and a carrier. An interspace is located between the carrier and the covering. The interspace is filled with an underfiller material is disclosed.

Abstract: A delay line calibration circuit is disclosed herein. The calibration circuit has an arbiter circuit having a unit for determining which of two signals that arrive first; a first and a second synchronous element each having an input for receiving a clock signal, and one of them having a unit for outputting the clock signal a clock period later; and a calibration circuit having inputs connected to the outputs of the arbiter circuit for receiving a signal from it indicative of whether the signal input to the arbiter circuit from the delay line is ahead or after the signal input to the arbiter circuit from the second element, the calibration circuit further being connected to the delay line for calibrating the delay line in accordance with the signal received from the arbiter circuit. The invention in at least one embodiment provides improved calibration of delay lines.

Abstract: Some embodiments have a semiconductor chip supported above a substrate, a filler layer encapsulating the semiconductor chip, a heat sink; and through contacts extending upwardly from the substrate nearly to an upper surface of the filler layer. In some embodiments of electronic packages, the through contacts separated from the heat sink by a trench cut into the upper surface of the filler layer, the through contacts intersecting one wall of the trench and the heat sink intersecting the other wall of the trench an electronic semiconductor package. A method of forming the package and a lead frame are also disclosed.

Abstract: Bottom electrodes of stacked capacitor DRAM cells are formed by depositing a metal layer on the side walls of trenches within a hard mask layer, which serves as a mold for the bottom electrode elements. Prior to depositing the hard mask layer a sacrificial first metal layer is disposed, which results in an electrically conductive surface on the semiconductor wafer. The mask layer is wet-etched to release the bottom electrode as free standing elements on the semiconductor surface. Using the conductive path provided by the first and the second metal layers, the bottom electrodes are polarized in a cleaning liquid bath during a wafer drying process. The generated repulsive electric field overcomes the attractive forces between the neighboring bottom electrode elements induced due to capillary effects of the liquids used for etching and cleaning.

Abstract: A power transistor includes a semiconductor layer an electrode layer. The semiconductor layer having a source zone, a drain zone spaced apart from the source zone in a lateral direction, a drift zone adjacent to the drain zone, and a body zone. The body zone is interposed between the drift zone and the source zone. The electrode layer is dielectrically insulated from the semiconductor layer, and includes a gate electrode divided into at least two sections and a field plate. The field plate is arranged at a first height level relative to the semiconductor layer. A first gate electrode section is arranged at least partially at a second height level, which is lower than the first height level relative to the semiconductor layer. A second gate electrode section, which is laterally displaced from the first gate electrode section, is disposed at a first intermediate level arranged between the first and second height levels.

Abstract: An improved ADSL system with improved data rate is disclosed. In one embodiment, the upstream data bit rate is increased by extending the upstream transmission band. In another embodiment, the downstream data is also increased by extending the downstream transmission band.

Abstract: In the case of a device for transmission of telephone signals via a data telecommunications network (2) the analogue signals of a telephone terminal are converted to digital signals for transmission via the data telecommunications network (2) and/or, vice versa, digital signals from the data telecommunications network (2) are converted to analogue signals for transmission via the telephone terminal. In order to monitor the operation of the device, advantageously digital signals arising within the device are analyzed. According to the invention a digital signal is acquired within the device and the characteristics of this, which characterize the amplitude and/or the frequency response of the acquired digital signal, are determined. The determined characteristics are sent out via the data telecommunications network (2). In this way the function of such conversion devices can also be monitored over a greater distance via the data telecommunications network (2) and signals arising therein can be analyzed.

Abstract: The stackable semiconductor device includes at least one first electrode on a top side and a large-area second electrode on an underside of a semiconductor chip. The semiconductor chip also includes a control electrode on one of: the top side or the underside. Through contact blocks are arranged on the edge sides of the semiconductor device, the through contact blocks including externally accessible external contact areas. The external contact area each includes at least one edge side contact area, a top side contact area and an underside contact area. At least one large-area external contact is arranged on the underside and/or on the top side of the semiconductor device.

Abstract: An apparatus for detecting an attack on an electric circuit, wherein the electric circuit includes a current consumption threshold value discriminator to determine whether current consumption of the electric circuit exceeds a predetermined threshold value or not, and to generate a binary current limitation signal depending therefrom. The apparatus includes a monitor for monitoring the binary current limitation signal over a predetermined time interval, in order to indicate a signal characterizing the current consumption of the electric circuit over the predetermined time interval, and a detector for detecting an attack on the electric circuit based on the monitoring signal.

Abstract: A semiconductor component includes flip-chip contacts arranged on a wiring structure of a semiconductor chip. The wiring structure includes at least one metallization layer and at least one dielectric insulation layer made of a low-k material with a relative permittivity ?r lower than the relative permittivity of a silicon dioxide. The flip-chip contacts are arranged on contact areas of an upper metallization layer and have a polymer core surrounded by a lead-free solder sheath.

Abstract: A pulsed static flip-flop comprises a first logic device which combines a logic signal with a pulsed signal and outputs a set signal, a second logic device which logically combines the logic signal with a complementary pulsed signal and outputs a reset signal; and a latch device comprising storage means which hold a logic hold level to be tapped off as a stored logic state of the logic signal. The logic hold level is adjustable to a first logic level by a first push-pull transistor controlled by the set signal and to a second logic level by a second push-pull transistor controlled by the reset signal.

Abstract: A detector circuit for detecting an external manipulation of an electrical circuit. The detector circuit includes a digital circuit which is sensitive to at least one of the effects of ionizing radiation or fluctuations of a supply voltage, and the output state of the digital circuit is indicative of an attack.

Abstract: A semiconductor component includes an integrated capacitor structure embodied at least partly in an electrically conductive plane and which is patterned such that a multiplicity of strip elements are present. A first group of strip elements constitutes a first electrode of the capacitor structure and a second group of strip elements constitutes a second electrode of the capacitor structure. The first strip elements together with the second strip elements being at least partly interlinked in one another, and at least one strip element may have a non-constant width along its length.

Abstract: A micromechanical capacitive converter and a method for manufacturing a micromechanical converter comprise a movable membrane and an electrically conductive face element in a carrier layer. The electrically conductive face element is arranged opposite the membrane above a cavity. The electrically conductive face element and the carrier layer are perforated by perforation openings. The opening width of the perforation openings corresponds approximately to the thickness of the carrier layer.

Abstract: A DC voltage converter having a plurality of outputs and a method for converting a DC voltage into a plurality of output-side DC voltages is disclosed. A control unit is used to drive a first and a second switch to drive an energy store in such a manner that a plurality of different output voltages are provided. The switches include field effect transistors, and at least the substrate terminal of one of these field effect transistors is connected to the control unit in order to be driven using a substrate potential in a manner dependent on an operating mode of the DC voltage converter. This makes it possible to provide different voltages both in an intermittent and in a continuous operating mode of the converter with, at the same time, a high degree of efficiency.

Abstract: Computer system for electronic data processing having programmable data transfer units used for transferring data from a first memory in which data is stored in a form of a multi-dimensional array to a second memory in such a way, that spatial or temporal locality for the transfer is established.