Patents Assigned to INFINEON
  • Device and method for regulating a transmission moment of a continuous transmission signal
    Patent number: 7263338
    Abstract: A comparator unit is used to compare an actual transmission time signal with a nominal transmission time signal and to produce a difference signal from the discrepancy, from which difference signal a correction signal is produced in a control unit. This correction signal is used to control a correction unit, which compresses or extends an applied input data signal, thus changing the phase angle of the output data signal so as to minimize the discrepancy between the transmission times. The discrepancy is corrected independently of the system clock, and the correction speed is set variably.
    Type: Grant
    Filed: February 21, 2003
    Date of Patent: August 28, 2007
    Assignee: Infineon Technologies AG
    Inventors: Robert Denk, Dietmar Wenzel, Robert Würth
  • Method for inspection of periodic grating structures on lithography masks
    Patent number: 7262850
    Abstract: The invention relates to a method for inspection of periodic structures on lithography masks using a microscope with adjustable illumination and an operating element for movement of a mechanical stage with the lithography mask attached to it in order to record images of the lithography mask at a computer-controlled location on the lithography mask. The position, the size and the pitch specification of the lithography mask are stored.
    Type: Grant
    Filed: December 12, 2003
    Date of Patent: August 28, 2007
    Assignee: Infineon Technologies AG
    Inventors: Wolfgang Dettmann, Roderick Koehle, Martin Verbeek
  • Bit line structure and production method thereof
    Patent number: 7262456
    Abstract: The disclosure relates to a bit line structure and an associated production method for the bit line structure. In the bit line structure, at least in a region of a second contact and a plurality of first contact adjoining the latter, an isolation trench is filled with an electrically conductive trench filling layer. The isolation trench connects to the first doping regions adjoining the second contact for the purpose of realizing a buried contact bypass line.
    Type: Grant
    Filed: November 14, 2005
    Date of Patent: August 28, 2007
    Assignee: Infineon Technologies AG
    Inventors: Ronald Kakoschke, Franz Schuler, Georg Tempel
  • Method for masking a recess in a structure having a high aspect ratio
    Patent number: 7261829
    Abstract: A method for selective masking is described. In this case, a filling material is applied to a structure which, as a function of the aspect ratio of the structure, forms cavities when the aspect ratio is high. The filling layer is then removed as far as the cavities and, using an etching process, filling material is removed completely from the recesses in which the cavities are formed. In this way, areas are exposed selectively.
    Type: Grant
    Filed: January 8, 2003
    Date of Patent: August 28, 2007
    Assignee: Infineon Technologies AG
    Inventors: Dirk Efferenn, Hans-Peter Moll
  • Compensation circuit for clock jitter compensation
    Patent number: 7262723
    Abstract: A compensation circuit for a digital/analogue converter, which is clocked by a clock signal comprising a jitter and converts a digital input data signal into an analogue output data signal comprising a jitter error due to said jitter, comprises a measurement circuit for measuring the jitter and a modelling circuit for generating a digital modelled jitter error signal which simulates the jitter error dependent on the measured jitter and the digital input data signal, wherein the digital modelled jitter error signal is subtracted from the digital input data signal.
    Type: Grant
    Filed: June 12, 2006
    Date of Patent: August 28, 2007
    Assignee: Infineon Technologies AG
    Inventors: Dietmar Straussnig, Bernd Rainer, Andreas Wiesbauer, Richard Gaggl, Martin Clara, Luis Hernandez
  • Integrated circuit, in particular integrated memory, and methods for operating an integrated circuit
    Patent number: 7263633
    Abstract: An integrated circuit, in particular, an integrated memory, contains a control circuit for ascertaining an operating state of the circuit. A self-repair circuit, which is connected to the control circuit, is used to implement self-test and self-repair operation for checking the functioning of, and repairing, defective circuit sections of the integrated circuit. After a supply voltage has been applied to the integrated circuit, the control circuit ascertains an operating state of the integrated circuit and, in a manner dependent thereon, the self-repair circuit is activated by the control circuit in a self-controlling manner in order to put the integrated circuit into a self-repair mode for implementing self-test and self-repair operation. The integrated circuit can be tested for its functionality and repaired even after being soldered onto a module substrate.
    Type: Grant
    Filed: May 25, 2004
    Date of Patent: August 28, 2007
    Assignee: Infineon Technologies AG
    Inventors: Evangelos Stavrou, Stephan Schröder, Manfred Pröll, Koen Van der Zanden
  • Memory circuit with flexible bitline-related and/or wordline-related defect memory cell substitution
    Patent number: 7263011
    Abstract: The inventive memory circuit comprises a main memory block and a substitution memory block for substitution of defect memory cells, with the substitution memory block being external to the main memory block. The substitution memory block is arranged to substitute at least one bitline-related or wordline-related set of memory cells being connected to the same bitline or wordline, respectively. Furthermore, the inventive memory circuit comprises redirection means for redirecting the access to a memory cell of the at least one respective substituted set of memory cells to the substitution memory block.
    Type: Grant
    Filed: October 7, 2005
    Date of Patent: August 28, 2007
    Assignee: Infineon Technologies AG
    Inventors: Vincent Gouin, Linda Hirel, Luc Palau
  • Method for generating a structure on a substrate
    Patent number: 7262118
    Abstract: The invention relates to a method for generating very short gate structures. In a method for generating a structure on a substrate in accordance with one embodiment of the invention, first of all a layer sequence of a first oxide layer, a first nitride layer and a second oxide layer is disposed onto the substrate. Subsequently, a portion of the second oxide layer and a portion of the first nitride layer is removed in order to expose a portion of the first oxide layer. Then, a part of the first nitride layer above the first oxide layer and below the second oxide layer is removed in order to expose the area of the structure.
    Type: Grant
    Filed: February 22, 2005
    Date of Patent: August 28, 2007
    Assignee: Infineon Technologies AG
    Inventor: Christian Herzum
  • Noninvasive method for characterizing and identifying embedded micropatterns
    Patent number: 7262837
    Abstract: The invention relates to a method for noninvasively characterizing embedded micropatterns which are hidden under the surface of a wafer down to 100 ?m. The micropatterns are identified with reference micropatterns from a previously produced reference library with the aid of their specific ellipsometric parameters.
    Type: Grant
    Filed: June 25, 2004
    Date of Patent: August 28, 2007
    Assignee: Infineon Technologies AG
    Inventors: Pierre-Yves Guittet, Ulrich Mantz, Eckhard Marx
  • Memory having test circuit
    Patent number: 7263638
    Abstract: A memory circuit comprises a memory and a first test circuit coupled to the memory. The first test circuit is configured to compare data read from memory cells with expected data for the memory cells to provide a first set of pass/fail signals for the memory cells, compress the first set of pass/fail signals for the memory cells into a second pass/fail signal, latch the second pass/fail signal in response to a data valid signal, maintain the latch of the second pass/fail signal if the second pass/fail signal indicates a failed test, combine the second pass/fail signal and a third pass/fail signal of a second test circuit to provide a fourth pass/fail signal, and pass the fourth pass/fail signal to a third test circuit.
    Type: Grant
    Filed: December 16, 2004
    Date of Patent: August 28, 2007
    Assignee: Infineon Technologies AG
    Inventor: Wolfgang Hokenmaier
  • Serial presence detect functionality on memory component
    Patent number: 7263019
    Abstract: Methods and apparatus for accessing serial presence detect data are provided. For some embodiments, serial presence detect logic is incorporated in memory devices, eliminating the need for a separate serial presence detect component.
    Type: Grant
    Filed: September 15, 2005
    Date of Patent: August 28, 2007
    Assignee: Infineon Technologies AG
    Inventors: Klaus Nierle, Martin Versen
  • Method and apparatus for determining a topology of a subscriber line loop
    Patent number: 7263121
    Abstract: An xDSL modem for data transmission between a central office and a customer device over a subscriber line includes a topology determining unit and a control unit. The topology determining unit is configured to determine the topology of the subscriber line. The control unit is configured to switch the xDSL modem between a normal mode for data transmission and a topology determining mode for determining the topology of the subscriber line.
    Type: Grant
    Filed: September 25, 2003
    Date of Patent: August 28, 2007
    Assignee: Infineon Technologies AG
    Inventors: Murat Belge, Rainer Storn
  • Thread ID in a multithreaded processor
    Patent number: 7263599
    Abstract: A multithreaded processor includes a thread ID for each set of fetched bits in an instruction fetch and issue unit. The thread ID attaches to the instructions and operands of the set of fetched bits. Pipeline stages in the multithreaded processor stores the thread ID associated with each operand or instruction in the pipeline stage. The thread ID are used to maintain data coherency and to generate program traces that include thread information for the instructions executed by the multithreaded processor.
    Type: Grant
    Filed: February 6, 2004
    Date of Patent: August 28, 2007
    Assignee: Infineon Technologies
    Inventors: Erik K. Norden, Robert E. Ober, Roger D. Arnold, Daniel F. Martin
  • METHOD FOR DETERMINING A SYSTEM OPERATING STATE
    Publication number: 20070198217
    Abstract: Provided is a method and an apparatus for detecting an operating state or a change in an operating state in a system in which at least one analog signal indicating the operating state is present. The method includes sampling of the analog signal or of a signal dependent on the analog signal for the purpose of providing a sampling signal. The method also includes generation of a transformation signal representing a spectral distribution from a number of signal values of the sampling signal, and comparison of the transformation signal with at least one reference signal representing a spectral distribution.
    Type: Application
    Filed: February 26, 2007
    Publication date: August 23, 2007
    Applicant: INFINEON TECHNOLOGIES AG
    Inventor: Thomas Kattwinkel
  • SYSTEM AND METHOD FOR SIGNAL TRANSMISSION
    Publication number: 20070195895
    Abstract: A system and method for signal transmission, a signal modulation and a signal demodulation device, and a method for signal transmission are disclosed. One embodiment includes transmitting a first pulse signal via a first line; and transmitting a second pulse signal complementary to the first pulse signal via a second line, wherein the point in time of the transmitting of the second signal relative to the point in time of the transmitting of the first signal is varied as a function of the respective digital data to be transmitted.
    Type: Application
    Filed: February 14, 2007
    Publication date: August 23, 2007
    Applicant: Infineon Technologies AG
    Inventor: Harry Siebert
  • DEVICE AND METHOD FOR PULSE WIDTH MODULATION
    Publication number: 20070194827
    Abstract: A device and a method for pulse width modulation is disclosed, wherein the temporal occurrence of both the respectively rising and the respectively falling edges of a pulse signal is varied.
    Type: Application
    Filed: February 9, 2007
    Publication date: August 23, 2007
    Applicant: INFINEON TECHNOLOGIES AG
    Inventor: Christoph Braun
  • CHIP MODULE HAVING A PROTECTION DEVICE
    Publication number: 20070194421
    Abstract: Some embodiments of a chip module comprise a substrate, a semiconductor chip on the substrate, and a first layer between the substrate and the semiconductor chip, the first layer having high reflectivity for electromagnetic waves. Methods of protecting a chip module from electromagnetic radiation by interposing a protective layer between the chip and the substrate are also disclosed.
    Type: Application
    Filed: December 22, 2006
    Publication date: August 23, 2007
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Marcus Janke, Peter Laackmann
  • METHOD FOR SYNCHRONIZING A CLOCK SIGNAL WITH A REFERENCE SIGNAL, AND PHASE LOCKED LOOP
    Publication number: 20070194819
    Abstract: A method for synchronizing a clock signal with a reference signal is disclosed. One embodiment has a first synchronization part which has a bit pattern having a particular clock period, a pause whose length is a multiple of this clock period plus a fraction of the clock period, and a second synchronization part having the particular clock period.
    Type: Application
    Filed: February 15, 2007
    Publication date: August 23, 2007
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Guenter Krasser, Thomas Duda
  • Wiring Substrate of a Semiconductor Component Comprising External Contact Pads for External Contacts and Method for Producing the Same
    Publication number: 20070194459
    Abstract: A wiring substrate of a semiconductor component includes: an underside with a wiring structure; a top side with cutouts; a rubber-elastic material arranged in the cutouts; and external contact pads arranged on the rubber-elastic material and configured to be coupled to external contacts. A method for producing a wiring substrate of this type, involves pressing the rubber-elastic material pads into a precursor of a polymer plastic during the production process.
    Type: Application
    Filed: February 20, 2007
    Publication date: August 23, 2007
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Michael Bauer, Rainer Steiner, Holger Woerner
  • Memory cell array and method for manufacturing it
    Patent number: RE39799
    Abstract: In a storage cell array, a first and a second line are provided which have a crossing point, at which a storage element with magnetoresistive effect is disposed. A yoke is provided which surrounds one of the lines and that contains magnetizable material with a permeability of at least 10. The yoke is disposed in such a way that a magnetic flow is closed substantially through the storage element.
    Type: Grant
    Filed: May 8, 2003
    Date of Patent: August 28, 2007
    Assignee: Infineon Technologies AG
    Inventor: Siegfried Schwarzl