Abstract: An apparatus and method for message management using nonvolatile analog signal recording and playback is disclosed. The device is an integrated circuit with interface circuitry for use as a peripheral device to a microcontroller or a microprocessor-based system. The integrated circuit is complete with differential analog inputs, auto attenuation to improve signal quality, filter, fixed references including a band gap reference, trimming, memory array, multiple closed loop sample and hold circuits, column device, row decoder, address counters, master oscillator, chip function timing circuits, and a serial peripheral interface (SPI) and circuits on a single chip. The integrated circuit is interfaced with a host microcontroller through the SPI. The host microcontroller can send a number of commands to the integrated circuit through the SPI for efficient message management. These commands include the basic commands to record or playback and various addressing and message cueing options.

Abstract: A gate-follower storage cell and a diode-connected storage cell for use in integrated circuit analog signal recording and playback is disclosed. The gate-follower storage cell is used in negative feedback mode to provide a one to one variation between the cell threshold and the gate voltage in the read mode. The diode-connected storage cell is connected in a diode configuration to provide a one-to-one variation between the cell threshold and the gate voltage in the read mode. The gate-follower or diode-connected storage cells may be implemented in a memory array for storing analog signals. In a preferred embodiment, the memory array provides wordlines which are accessible through column drivers. Each row or wordline is divided into a plurality of sector wordlines by inserting select transistors in the array. Each sector is driven by a column driver. In the read and programming modes, the sector wordlines are isolated from each other and are provided to the column drivers through additional select transistors.

Abstract: This invention utilizes the small cell size of the NAND storage cell structure in an analog storage and playback device. This is achieved, in part, by using a special, zero current storage cell, in which in the read mode, the cell loading current is waveshaped to attain an optimal dynamic range and to avoid the resistive effects of series parasitic resistances of other transistors in the source node or drain node, and to avoid the transistor conductance variations of all the transistors in the read path. The loading current is waveshaped to reduce possible overshoot and settling effects to achieve the fine output voltage resolution in an optimal sensing time. Details of the method and alternate embodiments are disclosed.

Abstract: MOS charge pump generation and regulation method and apparatus of the general type used in a non-volatile memory chip for generating high voltages (.about.20 v). This invention utilizes a current controlled oscillator to generate the clock for the charge pump voltage multiplier. The oscillator frequency is designed to compensate for process, temperature and power supply variations. The charge pump shunt regulator only utilizes regular low voltage NMOS and PMOS from a standard CMOS process. A reference voltage scheme is used in which a regular low voltage PMOS is used as a mirror diode (reference PMOS) to precisely realize a control voltage for the shunting NMOS without violating any breakdown mechanism, i.e. PMOS gated diode breakdown and P+ to n-well junction breakdown. A medium voltage level is also used to buffer the shunting NMOS transistors from gated diode breakdown.

Abstract: The voltage regulator of the present invention is configured in a negative feedback operational amplifier loop with diode connected p-MOS devices serving as a resistor divider to reduce the current loading to the voltage multiplier. Each diode connected p-MOS has its own well tied to its source so the VGS (gate to source voltage) of each p-MOS is precisely mirrored across the diode chain by the negative feedback action. This gives a precise voltage at the output of the regulator referenced to a reference voltage VREF. The regulator uses very little current without requiring large value resistors by utilizing the diode connected p-MOS transistors as a resistor divider.

Abstract: The present invention is an apparatus for storing a voltage level within a storage element such as an EEPROM. The apparatus includes a track and hold circuit that receives the voltage level to be stored and an integrator that determines a target voltage to be applied to the storage element representative of a voltage level less than the received voltage level. The apparatus further includes a voltage ramp circuit that applies a voltage ramp signal to the storage element for increasing an amount of voltage held in the storage element while simultaneously reading a voltage level of the storage element to determine whether the voltage of the storage element matches the target voltage and a comparator that deactivates the voltage ramp signal when the voltage of the storage element matches the target voltage.

Abstract: The present invention is an improvement in an analog storage device having a row of EEPROM cells. The improvement includes providing a reference EEPROM cell having first and second transistors connected in series, with a gate of the first transistor connected to a clear input line and a gate of the second transistor connected to a select input line. The improvement further includes providing a comparator having first and second inputs with the first input connected to a source of the second transistor and a second input connected to a reference voltage line and with an output of the comparator connected to the gate of the first transistor, wherein the gate of the first transistor is connected to gates of first transistors of each of the row of EEPROM cells.

Abstract: This invention utilizes the small cell size of the NAND storage cell structure in an analog storage and playback device. This is achieved, in part, by using a special, zero current storage cell, in which in the read mode, the cell loading current is waveshaped to attain an optimal dynamic range and to avoid the resistive effects of series parasitic resistances of other transistors in the source node or drain node, and to avoid the transistor conductance variations of all the transistors in the read path. The loading current is waveshaped to reduce possible overshoot and settling effects to achieve the fine output voltage resolution in an optimal sensing time. Details of the method and alternate embodiments are disclosed.

Abstract: The present invention discloses methods and apparatus for implementing a clocked high voltage switch involving MOS devices. The switching is from a high voltage source typically at 21V to ground. An intermediate voltage source typically at 11V is introduced for reducing the gated breakdown voltage requirement to approximately 10V. This reduced gated breakdown voltage requirement is easily met by special layout methods applied to various transistors in the circuit. The basic layout methods include the terminating of the field implant region near the N+P junction to expose the N+ diffusion over the P substrate to increase the junction breakdown and the gated diode breakdown, and the use of short channel length to reduce the threshold voltage.

Abstract: Message management methods and apparatus for the storage and selective playback, erase and other manipulation of messages such as voice messages in a voice message system are disclosed. The devices of the invention include analog signal sample and analog storage capabilities whereby messages may be stored in one or more message segment storage locations. A register stack in each device keeps track of the message number associated with the message segment stored in the respective message segment location so that message segments associated with a particular message may be located in sequence for seamless playback of the entire message. Message segment storage locations available for storing new messages may be identified by a flag identifying the same, such as by an otherwise unused message number stored in the associated stack register. Each device includes the capability of cascading with identical devices so as to extend the total record and playback time available.

Abstract: A redundancy circuit used in a non-volatile memory chip to increase the production yield due to manufacturing defects. The redundancy circuit includes a redundancy predecoder circuit, a source follower EEPROM (electrically erasable programmable read only memory) memory fuse, a scheme to use the column high voltage drivers (also known as page latch) to program the EEPROM fuses, a scheme to use the regular row decoder (also known as wordline driver or x-decoder) as the redundancy row decoder, and an out-of-bound address as a redundancy enable/disable signal.

Abstract: A fully differential output CMOS power amplifier suitable to be used in a non-volatile memory mixed mode chip for voice record and playback to drive a very low impedance load such as an 8 ohm speaker from a low voltage power supply. This fully differential CMOS power amplifier utilizes a voltage multiplying technique for the input stage, a level shift/gain stage, and a common mode feedback network. It also utilizes native n-MOS having a threshold voltage VT.apprxeq.0v for the folded cascode differential input, native n-MOS (VT.apprxeq.0v) for the source follower output stage, enhancement n-MOS (VT.apprxeq.0.7 v) for the common source output, and a voltage regulator using p-MOS diode connected devices for simulating a resistor divider to regulate the voltage multiplier output. The amplifier also includes a mechanism for crossover distortion reduction at the output driver stage, and a scheme to set the idle current in the output driver n-MOS transistors.

Abstract: An integrated circuit which operates to store an input analog signal within an analog storage device such as an EEPROM is disclosed. Initially, a target voltage is determined for applying to the memory cell with the target voltage set to about 90% of the input analog signal voltage. A high voltage ramp is applied to the memory cell to set the voltage of the memory cell to the target voltage. A read operation is simultaneously performed while the high voltage ramp is applied to detect the voltage stored on the cell and to terminate the application of the high voltage ramp once the target voltage is reached. Thereafter, a normal read operation is performed on the memory cell to detect the actual voltage of the cell. A new target voltage is determined based upon the actual voltage of the memory cell and the input analog signal voltage. The high voltage ramp is again connected to the memory cell to set the cell to the new target voltage while a simultaneous read operation is performed.

Abstract: Method and apparatus for adjustment and control of an iterative method of recording analog signals with on-chip trimming techniques for later playback. The invention allows setting of various parameters for the multi iterative programming technique after chip fabrication so as to allow tighter control and thus higher resolution analog signal sample storage in a given or minimum amount of time. Such parameters include, but are not limited to: the step down voltage from the coarse programming cycle to the fine programming cycle, the incremental voltage increase between each fine pulse, the pulse width of each fine pulse, the number of fine pulses, the incremental voltage increase between each coarse pulse, the pulse width of each course pulse, the number of coarse pulses, and the offset, VOS, which stops further coarse pulses and holds the last coarse level as a reference for the following fine cycle.

Abstract: Programmable non-volatile analog voltage source devices and methods wherein analog voltages may be sampled and stored in a non-volatile manner for output, typically through parallel output buffers. In one form and in a single integrated circuit, an input provided to the circuit may be stored at any analog storage location as determined by an address also provided to the circuit, the storage location determining at which of the outputs of the circuit the stored value will appear. While the storage, achieved by way of storage of differential voltages in floating gate MOSFET devices, is non-volatile, the same is also electrically alterable as desired. Various alternate embodiments and methods including the ability to address multiple pages of analog storage locations for storage of analog signals and selective parallel output of each page of the storage, output enable capabilities, parallel inputs and digital inputs are disclosed.

Abstract: For use in integrated circuit systems wherein both filter time constants and oscillator frequency each need a suitable reference, both the filter and the oscillator are referenced to common reference circuitry through a suitable control loop. Because the fundamental control parameters of the oscillator and the filter are time-period and time-constant respectively, the oscillator and the filter are implemented in a manner where the monolithic passive elements setting the fundamental control parameters (time-period and time-constant) are of the same type. This has the advantage of close tracking through process and ambient variations. Monolithic capacitors on the same chip are used as one of the common passive elements between the oscillator and the filter to set the time-period and time-constants, respectively, adjustable through adjustment of control currents.

Abstract: The present invention discloses methods and apparatus for implementing a single-transistor cell EEPROM array for analog or digital storage. The single-transistor storage cell is made possible by continuously maintaining a net negative charge on the floating gate of the EEPROM storage transistor. Furthermore, according to the present invention, a dense layout of the single-transistor cells is possible by sharing a common diffusion region between the transistors located in the same row and the transistors located in one adjacent row. This common diffusion region functions as a source in the erase and program modes, and as a drain in the read mode. Moreover, the common diffusion feature of the present invention allows the use of a single level of metal in distributing the various operating voltages to the EEPROM storage transistors. Further, utilizing a single level of metal allows for a simple and dense fabrication and also reduces the parasitic capacitances in the EEPROM storage array.

Abstract: For use in integrated circuit systems wherein both filter time constants and oscillator frequency each need a suitable reference, both the filter and the oscillator are referenced to common reference circuitry through a suitable control loop. Because the fundamental control parameters of the oscillator and the filter are time-period and time-constant respectively, the oscillator and the filter are implemented in a manner where the monolithic passive elements setting the fundamental control parameters (time-period and time-constant) are of the same type. This has the advantage of close tracking through process and ambient variations. Monolithic capacitors on the same chip are used as one of the common passive elements between the oscillatorand the filter to set the time-period and time-constants, respectively, adjustable through adjustment of control currents.

Abstract: Integrated circuit system for analog signal recording and playback having improved performance and a very high level of integration. The integrated circuit is complete with preamplifier, automatic gain control, filter, fixed references including a band gap reference, trimming, power output amplifier, memory array, multiple closed loop sample and hold circuits, column decoder, column driver, row decoder, address counters, master oscillator and chip function timing circuits including sample clock, charge pumps, high voltage regulator and waveshapers, low VCC detector, power-on reset and recording reference circuits on a single chip. The system uses a writable analog reference scheme to put many error sources in the common mode, and provides a double ended output for maximum power output in a limited voltage range, and to allow direct connection to a speaker.

Abstract: Source follower storage cell and improved method and apparatus for iterative write for integrated circuit analog recording and playback which provides increased resolution in the stored signal and increased accuracy and stability of the storage and readout capabilities of the device. The storage cell is configured wherein the electrically alterable MOS storage device is connected in a source follower configuration, which provides a one to one relationship between the variation in the floating gate storage charge and the variation in the output voltage, and for high load resistance, relative insensitivity to load characteristics. The write process and circuitry provides a multi iterative programming technique wherein a series of coarse pulses program a cell to the approximate desired value, with a series of fine pulses referenced to the last coarse pulse being used for programming the respective cell in fine increments to a desired final programming level. Still finer levels of programming can be used.