Patents Assigned to Inmos Limited
  • Patent number: 6614098
    Abstract: A method of fabricating a tungsten contact in a semiconductor device comprises providing an oxide layer on a region of a silicon substrate; depositing a sealing dielectric layer over the oxide layer; and depositing an interlevel dielectric layer over the sealing layer. The interlevel dielectric layer, the sealing dielectric layer and the oxide layer are then etched through as far as the substrate thereby to form a contact hole and to expose the said region. A dopant is implanted into the said region whereby the implanted dopant is self-aligned to the contact hole. The substrate is thermally annealed. Tungsten is selectively deposited in the contact hole and an interconnect layer is deposited over the deposited tungsten contact. The invention also provides a semiconductor device which incorporates a tungsten contact and which can be fabricated by the method.
    Type: Grant
    Filed: December 21, 1999
    Date of Patent: September 2, 2003
    Assignee: Inmos Limited
    Inventors: Howard Charles Nicholls, Michael John Norrington, Michael Kevin Thompson
  • Patent number: 6100581
    Abstract: A semiconductor device comprising at least one semiconductor chip, the or each semiconductor chip having a plurality of chip bonding pads, a package which encloses the at least one semiconductor chip, a first level interconnect comprising a printed circuit which overlies the at least one semiconductor chip in the package and extends externally of the package to provide a plurality of outer leads, and a second level interconnect comprising means for electrically connecting the chip bonding pads to selected contacts on the printed circuit, which contacts overlie the at least one semiconductor chip. The invention also relates to a method of manufacturing such a semiconductor device and to a method of assembling a semiconductor assembly.
    Type: Grant
    Filed: October 21, 1994
    Date of Patent: August 8, 2000
    Assignee: Inmos, Limited
    Inventors: Elwyn Paul Michael Wakefield, Christopher Paul Hulme Walker
  • Patent number: 6034419
    Abstract: A method of fabricating a tungsten contact in a semiconductor device comprises providing an oxide layer on a region of a silicon substrate; depositing a sealing dielectric layer over the oxide layer; and depositing an interlevel dielectric layer over the sealing layer. The interlevel dielectric layer, the sealing dielectric layer and the oxide layer are then etched through as far as the substrate thereby to form a contact hole and to expose the said region. A dopant is implanted into the said region whereby the implanted dopant is self-aligned to the contact hole. The substrate is thermally annealed. Tungsten is selectively deposited in the contact hole and an interconnect layer is deposited over the deposited tungsten contact. The invention also provides a semiconductor device which incorporates a tungsten contact and which can be fabricated by the method.
    Type: Grant
    Filed: December 6, 1993
    Date of Patent: March 7, 2000
    Assignee: Inmos Limited
    Inventors: Howard Charles Nicholls, Michael John Norrington, Michael Kevin Thompson
  • Patent number: 5742783
    Abstract: Computer appratus includes an instruction execution unit (13) having a plurality of functional units (14,16) each arranged to execute at least part of an instruction and instruction issuing circuitry (10,12) for issuing simultaneously a group of separate compatible instructions to the execution unit (13) the circuitry (12) having means for classifying each instruction in dependence on the or each functional unit required for execution of that instruction and means for testing the classification of successive instructions and selecting a group which according to their classification are compatible for simultaneous issue to the execution unit (13) without conflicting demands on any function unit (14,16) in the execution unit.
    Type: Grant
    Filed: August 22, 1994
    Date of Patent: April 21, 1998
    Assignee: Inmos Limited
    Inventors: Saeid Azmoodeh, Peter Malcolm Keith Boffey, Richard Matthew Forsyth, Brian Jeremy Parsons
  • Patent number: 5670820
    Abstract: In a semiconductor polycide resistive element having a first region of polysilicon of one conductivity type and second regions of polysilicon of opposite conductivity type, with silicide overlying the polysilicon but not the first region, the edges of the silicide are spaced apart from the boundaries between the opposite conductivity types.
    Type: Grant
    Filed: August 15, 1994
    Date of Patent: September 23, 1997
    Assignee: Inmos Limited
    Inventors: Richard Norman Campbell, Michael Kevin Thompson, Elizabeth Ann Smith
  • Patent number: 5602055
    Abstract: A semiconductor device comprising a silicon substrate, an oxide layer on the silicon substrate, a doped polysilicon region disposed on the oxide layer, a dielectric layer which has been deposited over the doped polysilicon region and the silicon substrate, a contact hole which is formed in the dielectric layer and extends over respective laterally adjacent portions of the doped polysilicon region and the silicon substrate and a contact which has been selectively deposited in the contact hole which electrically connects the said portions together.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: February 11, 1997
    Assignee: Inmos Limited
    Inventors: Howard C. Nicholls, Michael J. Norrington
  • Patent number: 5586116
    Abstract: In a network with switching elements, a transmission path is found in that each destination address at a switching element is allocated a group of outputs via which messages can be transmitted to this destination address. Within this group of outputs, a search is made for a free output and messages are buffered as long as there is no output free within this group. Thus, in the process, there is deliberately no exclusive use of a specific output and each destination address is allocated a plurality of possible outputs. As a result, the probability of a blockage of outputs is reduced and the network throughput is increased.
    Type: Grant
    Filed: June 24, 1993
    Date of Patent: December 17, 1996
    Assignees: Siemens Aktiengesellschaft, INMOS Limited
    Inventors: Holm Hofestadt, Erwin Reyzl, Peter Thompson
  • Patent number: 5574875
    Abstract: A fully associative cache memory for virtual addressing comprises a data RAM (50), a first CAM cell array (51) for holding virtual page addresses which each require address translation to identify a physical page in a main memory, a second CAM cell array (52) holding line or word in page addresses which remain the same for virtual and physical addresses, a physical address memory (53) for holding physical page addresses for the main memory corresponding to virtual page addresses in said first array (51), said first array (51) being connected both to said physical address memory (52) to access said physical address memory in response to a hit output from said first CAM cell array and to control circuitry (57) coupled between said first and second arrays (51,52) and the data RAM (50) to access the data RAM (50) in response to hit outputs from both said first and second CAM cell arrays (51,52).
    Type: Grant
    Filed: March 12, 1993
    Date of Patent: November 12, 1996
    Assignee: Inmos Limited
    Inventors: Anthony I. Stansfield, Catherine L. Barnaby, Richard J. Gammack, Roger M. Shepherd
  • Patent number: 5541434
    Abstract: A semiconductor device comprising a silicon substrate, an oxide layer on the silicon substrate, a doped polysilicon region disposed on the oxide layer, a dielectric layer which has been deposited over the doped polysilicon region and the silicon substrate, a contact hole which is formed in the dielectric layer and extends over respective laterally adjacent portions of the doped polysilicon region and the silicon substrate and a contact which has been selectively deposited in the contact hole which electrically connects the said portions together.
    Type: Grant
    Filed: September 10, 1993
    Date of Patent: July 30, 1996
    Assignee: Inmos Limited
    Inventors: Howard C. Nicholls, Michael J. Norrington
  • Patent number: 5525938
    Abstract: A ring oscillator having an odd number of single ended stages, each stage including two transistors connected as a current mirror. The stage provides for low-voltage performance and improved process tolerance characteristics.
    Type: Grant
    Filed: May 5, 1995
    Date of Patent: June 11, 1996
    Assignee: INMOS Limited
    Inventors: Trevor K. Monk, Andrew M. Hall
  • Patent number: 5512783
    Abstract: A semiconductor chip package comprising at least one semiconductor chip disposed in a package and a plurality of first and second pins extending from the package, which first pins are electrically connected to the at least one semiconductor chip and are adapted to conduct signals between the at least one semiconductor chip and external circuitry, the first pins being divided into a plurality of groups, each group representing a respective signal type, and which second pins are not electrically connected to the at least one semiconductor chip, the first pins of at least one group and the second pins being asymmetrically disposed along edges of the package and the remaining groups of first pins being symmetrically disposed along edges of the package. The invention also provides a stacked module of the semiconductor chip packages.
    Type: Grant
    Filed: October 7, 1992
    Date of Patent: April 30, 1996
    Assignee: INMOS Limited
    Inventors: Elwyn P. M. Wakefield, Christopher P. H. Walker
  • Patent number: 5506437
    Abstract: A microcomputer comprises an integrated circuit device with processor and memory and communication links arranged to provide non-shared connections to similar links of other microcomputers. The communication links include message synchronization and permit creation of networks of microcomputers with rapid communication between concurrent processes on the same or different microcomputers.
    Type: Grant
    Filed: May 24, 1993
    Date of Patent: April 9, 1996
    Assignee: Inmos Limited
    Inventors: Michael D. May, Jonathan Edwards, David L. Waller
  • Patent number: 5491359
    Abstract: A microcomputer comprises an integrated circuit device with processor and memory and communication links arranged to provide non-shared connections to similar links of other microcomputers. The communication links include message synchronization and permit creation of networks of microcomputers with rapid communication between concurrent processes on the same or different microcomputers.
    Type: Grant
    Filed: May 24, 1993
    Date of Patent: February 13, 1996
    Assignee: INMOS Limited
    Inventors: Michael D. May, Jonathan Edwards, David L. Waller
  • Patent number: 5452467
    Abstract: A microcomputer includes an on-chip processor with at least 1K bytes of high density RAM on-chip together with isolation regions to protect the RAM from noise from transistors on-chip operating independently of the RAM.
    Type: Grant
    Filed: May 24, 1993
    Date of Patent: September 19, 1995
    Assignee: Inmos Limited
    Inventors: Michael D. May, Jonathan Edwards, David L. Waller
  • Patent number: 5449640
    Abstract: A method of fabricating an electrical contact in a semiconductor device comprises providing on an underlying silicon substrate a reflowable interlevel dielectric material having a contact opening exposing a contact region of the silicon substrate. The silicon substrate and the interlevel dielectric material are heated by a rapid thermal anneal in an oxygen-containing atmosphere thereby to grow an oxide control layer in the contact region and to reflow the dielectric material. A layer of transition metal is deposited over the reflowed dielectric material and the control layer and at least part of the transition metal layer is converted into a metallurgic barrier.
    Type: Grant
    Filed: July 19, 1991
    Date of Patent: September 12, 1995
    Assignee: INMOS Limited
    Inventors: Paul A. Hunt, Ian M. Liles, David R. Guite
  • Patent number: 5430388
    Abstract: A switching circuit for an FET transistor includes a controlled current circuit coupled to the gate of the FET. The input to the controlled current circuit represents a desired rate of change of gate voltage of the FET and is generated by a circuit responsive to the average specific transconductance of two FETs of similar specific transconductance operating at different drain circuit densities.
    Type: Grant
    Filed: June 11, 1993
    Date of Patent: July 4, 1995
    Assignee: Inmos Limited
    Inventors: Andrew M. Hall, Trevor K. Monk
  • Patent number: 5422308
    Abstract: A method of fabricating a tungsten contact in a semiconductor device comprises providing an oxide layer on a region of a silicon substrate; depositing a sealing dielectric layer over the oxide layer; and depositing an interlevel dielectric layer over the sealing layer. The interlevel dielectric layer, the sealing dielectric layer and the oxide layer are then etched through as far as the substrate thereby to form a contact hole and to expose the said region. A dopant is implanted into the said region whereby the implanted dopant is self-aligned to the contact hole. The substrate is thermally annealed. Tungsten is selectively deposited in the contact hole and an interconnect layer is deposited over the deposited tungsten contact. The invention also provides a semiconductor device which incorporates a tungsten contact and which can be fabricated by the method.
    Type: Grant
    Filed: December 6, 1993
    Date of Patent: June 6, 1995
    Assignee: Inmos Limited
    Inventors: Howard C. Nicholls, Michael J. Norrington, Michael K. Thompson
  • Patent number: 5422881
    Abstract: A method of routing messages through a network is described in which a message packet is dispatched with two node indicators through the network including a succession of routing switches. When the message packet reaches a routing switch identified by the first node indicator, that routing switch deletes the first node indicator and the second node indicator is then used to route the message packet through the network.
    Type: Grant
    Filed: September 20, 1993
    Date of Patent: June 6, 1995
    Assignee: Inmos Limited
    Inventors: Michael D. May, Brian J. Parsons, Peter W. Thompson, Chistopher P. H. Walker
  • Patent number: 5422879
    Abstract: A communications device, particularly but not exclusively for use with a routing circuit, transmits and receives message packets. An output buffer converts data and flow-control information into a plurality of bit sequences and transmits them at a predetermined frequency. An input buffer decodes informing sequences into data items and flow control information. The input buffer can store the data items and count them and transmit flow control information to the output buffer.
    Type: Grant
    Filed: January 12, 1993
    Date of Patent: June 6, 1995
    Assignee: Inmos Limited
    Inventors: Brian J. Parsons, Peter W. Thompson
  • Patent number: 5412368
    Abstract: A method of comparing a first multibit digital signal with a second multibit digital signal wherein to increase speed of obtaining an output signal said method comprises inputting input signals for each of said first and second signals and forming a respective codeword for each input signal, each codeword being at least one bit longer than the respective input signal and formed by the same error correcting code for both signals to provide increased minimum Hamming distance for the respective codewords, comparing respective bit locations of the codewords to form a plurality of match indicating signals for respective bit locations thereby indicating any mismatch by a mismatch at at least two bit locations, supplying said match indicating signals in parallel to gating circuitry arranged to provide an output indicating a match or mismatch between said codewords, said output being provided with a time delay less than that required for a single bit mismatch.
    Type: Grant
    Filed: June 29, 1993
    Date of Patent: May 2, 1995
    Assignee: Inmos Limited
    Inventors: Richard J. Gammack, Catherine L. Barnaby, Anthony I. Stansfield