Abstract: A programmable logic device is disclosed which can be used either as a look-up table logic device or as a logic function generator. This enables combinations to be provided such as the combination of a look-up table with a fixed gate field programmable gate array.

Abstract: There is described clock generation circuitry comprising: a plurality of sequentially connected delay devices, a first one of which is coupled to receive the first clock signal, each delay device being operable to produce a trigger signal and an output signal at a predetermined time after receiving a trigger signal from the previously connected delay device; control circuitry common to said delay devices for controlling said predetermined time interval; and output circuitry coupled to receive the output signals of the delay devices to produce therefrom said second clock signal.

Abstract: In an integrated circuit, a multiplexor receives incoming data at a first rate and is controllable by a high rate clock signal to output that data serially at a second, higher rate. A processing device receives the data from the multiplexor at the higher rate and is controllable by a high rate clock signal to process that data. Clock generation circuitry receives a first clock signal at the first rate and produces the high rate signal for the processing device and the multiplexor. Clock generation circuitry includes sequentially connected delay devices, one connected to receive the first clock signal. Each delay device produces a trigger signal and an output signal a predetermined time after receiving the trigger signal from the previous delay device. A control circuit is common to the delay devices for controlling the predetermined time interval. An output circuit receives the output signals of the delay devices and produces the high rate clock signal.

Abstract: A communication interface for interconnecting a computer with at least one other device has a link output circuit and a link input circuit. A link output on one device is connected to a link input on another device by a data line and a parallel strobe line. Data is transmitted on the data line in serial bit strings forming a succession of tokens of predetermined lengths. Signal transitions are provided on the parallel strobe line where no signal transition occurs on the data line. Each token includes a bit indicating the length of the token and a parity bit providing a check on bits in a preceding token.

Abstract: A method of encoding data for transmission between computer devices is disclosed in which data is encoded into a plurality of sequences, each sequence containing an equal number of ones and zeros and being of a predetermined bit length. There is a finite set of the permutations of equal numbers of ones and zeros in that predetermined bit length. One subset of the finite set is selected for use as data codes and a second subset is selected for use as control codes.

Abstract: A memory is provided with at least one temporary store and write abort circuitry having a control signal store and gating circuitry responsive to an output from the control signal store. Write circuitry loads data and an associated address in the temporary store during one write cycle and transfer circuitry transfers the data to the associated address during a subsequent write cycle when the write operation is not to be aborted. Read circuitry includes a comparator for comparing a read address with an address in the temporary store and transfer circuitry includes selection circuitry to select an output of data either from the temporary store or the memory dependent on the output of the comparator circuitry, an output from the temporary store being prevented if the control signal store indicates that the write operation is to be aborted.

Abstract: A voltage controlled oscillator comprises a plurality of differential amplification stages each arranged to introduce a phase shift between its differential input signal and its differential output signal. The frequency at which the desired phase shift occurs can be controlled by adjusting the control signal Vc. The stages are arranged such that the output of one amplifier becomes the input to the next amplifier, making the phase shift additive. Further, a phase shift of 180.degree. may be introduced by inverting the output from one stage before inputting it to the next stage. The total phase shift introduced by the stages is 360.degree.. In this way, an oscillating signal of varying phase shift is produced at the output of each stage. Each stage comprises a standard differential amplifier, well known in the art, having a matched pair of p-channel transistors and a matched pair of n-channel transistors.

Abstract: A method and apparatus are disclosed for filtering ghost signals from a video signal sequence. Storage circuitry stores a representation of a reference signal, Input circuitry inputs video signals from the video signal sequence. Comparison circuitry compares the stored representation of the reference signal with a reference signal received in the video signal sequence at the input circuitry, thereby to detect ghosts. Filter coefficient generating circuitry is connected to the comparison circuitry to generate a frequency domain representation of filter coefficients dependent on ghost signals detected. A forward Fourier transform pipeline is connected to the input circuitry to form a frequency domain representation of data in the video signal sequence received by the input circuitry. Product forming circuitry forms in the frequency domain a product of the filter coefficients with the frequency domain representation of the data in the video signal sequence.

Abstract: A memory circuit comprises a plurality of memory cells (2) arranged in rows and columns, the cells in each row being connected to a common wordline (4) and the cells in each column being connected between a pair of bit lines (6,8) across which a voltage differential is developed when a memory cell is accessed to be read; and a timing circuit (16) for producing a timing signal to control further circuitry in dependence on said voltage differential achieving a predetermined value. The memory circuit has a dummy bit line connected to a column of dummy cells, each dummy cell having the same structure as a memory cell.

Abstract: An integrated circuit including a multiplexor connected to receive incoming data at a first rate and controllable by a high rate clock signal to output that data serially at a second, higher rate; a processing device coupled to receive data output from the multiplexor at the higher rate and controllable by a high rate clock signal to process that data; and clock generation circuitry connected to receive a first clock signal at said first rate and operable to produce therefrom said high rate clock signal to be supplied to the processing device and to the multiplexor.

Abstract: A microcomputer comprises an integrated circuit device with processor and memory and communication links arranged to provide non-shared connections to similar links of other microcomputers. The communication links include message synchronisation and permit creation of networks of microcomputers with rapid communication between concurrent processes on the same or different microcomputers.

Abstract: Digital signal processing circuitry for calculating separable two dimensional linear transforms on blocks of data elements includes two processors coupled as a linear pipeline. Each processor carries out a one dimensional linear transform effecting multiplication of transform coefficients by repeated addition in a carry save adder network to form a plurality of inner products. The two processors may effect simultaneously different transforms on respective blocks of data.

Abstract: A method of fabricating a polycide semiconductor element in which a lift-off mask is formed on a first region of a layer of polysilicon. A first dopant is implanted into second regions of the polysilicon which are adjacent the first region, the first region being masked from implantation by the lift-off mask. A layer of silicide is forced over the implanted regions and the lift-off mask and then the lift-off mask and the respective part of the layer of silicide which is deposited thereover are removed thereby to expose the first region. The method may be used to fabricate a resistive device in a polycide semiconductor element. There is also disclosed a semiconductor element, e.g. a resistive device, made by the method.

Abstract: A semiconductor chip package comprising at least one semiconductor chip disposed in a package and a plurality of first and second pins extending from the package, which first pins are electrically connected to the at least one semiconductor chip and are adapted to conduct signals between the at least one semiconductor chip and external circuitry, the first pins being divided into a plurality of groups, each group representing a respective signal type, and which second pins are not electrically connected to the at least one semiconductor chip, the first pins of at least one group and the second pins being asymmetrically disposed along edges of the package and the remaining groups of first pins being symmetrically disposed along edges of the package. The invention also provides a stacked module of the semiconductor chip package.

Abstract: A multi-stage adder has a plurality of parallel inputs some fed to one stage of the adder and other inputs fed to a next stage of the adder. To effect selective inversion of a pair of inputs one of the pair is connected to one stage and the other of the pair is connected to the next stage. A cross-over switch is provided on both inputs so that their connection to the two successive stages can be interchanged.

Abstract: A memory circuit comprises a memory array having a plurality of memory cells arranged in rows and columns. Column select circuits enable access to the columns in the array. Each column select circuit is associated with a respective group of the columns and is arranged to access a selected one of the columns in the respective group. At least one spare memory column is provided. Also included are a plurality of read/write circuits associated respectively with the groups, and with the spare memory column, for reading or writing data bits between a data bus and the columns selected by the column selected circuits. Routing circuitry is connected between the read/write circuits and the data bus and is programmable with information identifying at least one faulty column.

Abstract: A decoder having a plurality of outputs (R.sub.0 -Rn) each associated with a particular output valve is arranged to add together two binary numbers (A, B) and to select one of the outputs in dependence on the result of the sum. The decoder comprises a plurality of logic circuits each arranged to receive respective bits of both first and second binary numbers to be added together. The logic circuits are arranged to provide, for each output value, a respective result in dependence on the logic states of respective bits of binary numbers representing that particular output value of the decoder. The logic means determines when a predetermined condition is satisfied by the results of the logic circuits associated with an output value of the decoder, whereby that output value is selected.

Abstract: A routing switch includes an input for receiving serial packets from a source node in a computer network, a plurality of outputs each designating a respective range of destination node identifications, switch circuitry for selectively interconnecting said input to a selected one of said outputs and header reading circuitry for reading the header portion of a packet received at the input prior to receiving all of the packet. The header reading circuitry is coupled to the switch circuitry to connect to said input one of said outputs having a node identification range including the node identification of said header portion.There is also provided a computer network, having a plurality of computer devices and at least one routing switch, and a method of routing messages through such a network.

Abstract: A routing switch includes an input for receiving serial packets from a source node in a computer network, a plurality of outputs, switch circuitry for selectively interconnecting said input to a selected one of said outputs and header reading circuitry for reading the header portion of a packet received at the input prior to receiving all of the packet. The switch also has a random header generator which produces header portions generated at random which are then read by the header reading circuitry. The header reading circuitry is coupled to the switch circuitry to connect to said input one of said outputs in dependence on said random header. The random header portion is then discarded at the routing switch identified thereby to reveal the original header.

Abstract: A current mirror curcuit has an actively controllable feedback element in the form of a p-channel field effect transistor (28). The p-channel transistor 28 has its gate connected to the output of a differential amplifier (12). The opamp 12 is connected to form a feedback loop within the current mirror circuit. The negative input (14) of the opamp (12) is connected to receive at node (16) the drain voltage V1 of the first transistor (24). The positive input (18) of the opamp (12) is connected to receive at node (20) the drain voltage (V2) of the second transistor (26). The purpose of the opamp 12 is to tend to equalize the drain voltages V1 and V2 of the first and second transistors 24, 26. If the drain voltage V2 of the second transistor 26 increases relative to the drain voltage V1 of the first transistor 24 the output signal Vo of the opamp 12 will be such as to reduce Vgs of the transistor 28 and hence Ids thereby to reduce the drain voltage V2 of the second transistor 26.