Abstract: Systems and methods are provided for concatenated error-correcting coding. An apparatus may include a Low-Density Parity-Check (LDPC) decoder configured to perform an iterative LDPC decoding process on bits of an LDPC codeword, a Bose-Chaudhuri-Hocquenghem (BCH) decoder coupled to the LDPC decoder and a BCH scheduler coupled to the LDPC decoder and the BCH decoder. The LDPC codeword may be generated by LDPC encoding a Bose-Chaudhuri-Hocquenghem (BCH) codeword and the BCH codeword may be generated by BCH encoding a data unit. The BCH scheduler may be configured to determine whether a triggering condition for the BCH decoder is met after each iteration of the iterative LDPC decoding process and activate the BCH decoder to operate on an intermediate decoding result of the LDPC decoder if the triggering condition for the BCH decoder is met.

Abstract: The present disclosure relates to a storage device and a storage system. The device comprises a storage, a storage controller, a control module, and a buffer module. The control module is configured to: when receiving a data read-write instruction, update the data read-write instruction by using a virtual address; apply for K buffer units in the buffer module; perform a write operation on the K buffer units by using data to be read and written; and when any of the K buffer units is full, directly start data transmission of the full buffer unit. By using the virtual storage address and by employing data block management, the present disclosure can update and forward an NVMe I/O command without applying for a storage space in advance, and can start data block transmission without checking the completion message.

Abstract: Systems, apparatus and methods are provided for performing cache program operations in a non-volatile storage system. A method may comprise issuing a first cache program operation from a storage controller to a non-volatile storage device to write data to a first regular block, writing the data to the first regular block and a copy of the data to a backup block, determining that a program error has occurred while writing the data to the first regular block, asserting the program error to the storage controller, retrieving a mapping between the first regular block and the backup block, issuing a read operation to read the copy of the data from the backup block, reading the copy of the data from the backup block and issuing a second cache program operation to write the data to a second regular block and marking the first regular block as defective.

Abstract: Systems, apparatus and methods are provided for managing a removable solid state storage system for data loss prevention. A method may include maintaining a standby mode for a timer of the removable solid state storage system until the removable solid state storage system is disconnected from an external power supply, setting an operation time interval on the timer, using the timer to count how long the removable solid state storage system has been disconnected, sending an interrupt to a storage controller of the removable solid state storage system from the timer when the timer counts to the operation time Interval, and performing data loss prevention operations using a power supplied by a removable battery.

Abstract: Systems and methods are provided for decoding data read from non-volatile storage devices. A method that may include decoding a first codeword read from a storage location of a non-volatile storage device using a first decoder without soft information, determining that the first decoder has failed to decode the first codeword, decoding the first codeword using a second decoder without soft information, determining that the second decoder has succeeded in decoding the first codeword, generating soft information associated with the storage location using decoding information generated by the second decoder and decoding a subsequent codeword from the storage location using the soft information associated with the storage location. The second decoder may be more powerful than the first decoder.

Abstract: Systems, apparatus and methods are provided for temperature assisted non-volatile storage device management in a non-volatile storage system. In one embodiment, a non-volatile storage system may comprise a temperature sensor, a non-volatile storage device and a processor. The processor may be configured to obtain a read-out from the temperature sensor, generate a predicted real-time on-die temperature for the non-volatile storage device based on the read-out, generate an estimated threshold voltage for reading data stored in the non-volatile storage device based on the predicted real-time on-die temperature and conduct a local sweep of a reference voltage using the estimated threshold voltage as a starting point to obtain a final read reference voltage with a minimum read bit error rate.

Abstract: Systems, apparatus and methods are provided for low temperature management of a storage system. An apparatus may include a temperature sensor to generate a temperature reading, a timer configured with a time interval, a backup battery, one or more non-volatile memory (NVM) devices and a storage controller. The storage controller may be configured to: maintain a standby mode for low temperature management until a host electronic system has been turned off, start the timer and check the temperature reading when the host electronic system is turned off, determine that the temperature reading is below a temperature threshold, set the time interval based on the temperature reading, receive an interrupt from the timer when the timer counts to the time Interval, and perform low-temperature management operations for data stored in the one or more NVM devices using power supplied by the backup battery.

Abstract: Systems, apparatus and methods are provided for logical-to-physical (L2P) address translation. A method may comprise receiving a request for a first logical data address (LDA), and calculating a first translation data unit (TDU) index for a first TDU. The first TDU may contain a L2P entry for the first LDA. The method may further comprise searching a cache of lookup directory entries of recently accessed TDUs using the first TDU index, determining that there is a cache miss, generating and storing an outstanding request for the lookup directory entry for the first TDU in a miss buffer, retrieving the lookup directory entry for the first TDU from an in-memory lookup directory, determining that the lookup directory entry for the first TDU is not valid, reserve a TDU space for the first TDU in a memory and generating a load request for the first TDU.

Abstract: Systems, apparatus and methods are provided for performing program operations in a non-volatile storage system. In one embodiment, there is provided a method that may comprise categorizing active storage blocks of a non-volatile storage device into a robust group and a less-robust group based on a number of factors including page error count, program time and number of Program/Erase (P/E) cycles; determining that a cache program operation needs to be performed; selecting a first storage block from the robust group to perform the cache program operation; determining that a regular program operation needs to be performed; and selecting a second storage block from the less-robust group to perform the regular program operation.

Abstract: The present disclosure relates to a firmware security verification method and device, including a processor and a read-only memory for storing instructions executable by the processor. While executing the instructions, the processor implements the following steps: acquiring firmware data and a digital signature; verifying the digital signature with a pre-stored public key; and running the firmware data upon determining that the digital signature passes the verification. With the firmware security verification method and device provided in embodiments of the present disclosure, the security of the firmware data can be acquired before the running of firmware.

Abstract: A method for finding an optimum read voltage includes acquiring difference values between state bit counts of different positions. A direction for finding the optimum read voltage is determined based on the difference values. An offset for finding the optimum read voltage is determined based on correspondence between a difference value of bit count and offset. Reading is performed with the offset applied to a current read reference voltage, wherein upon read-success, the current reference voltage superimposed with the offset is the optimum read voltage, and upon read-error, new first and second positions are obtained based on the direction and the offset for finding the optimum read voltage until reading becomes successful.

Abstract: The present disclosure provides a packaging-level chip and a chip module packaged with a magnetic cover, and an electronic product. The packaging-level chip packaged with a magnetic cover comprises a die, a packaging material, a substrate and a magnetic cover. The packaging material is packaged on the outside of the die which is arranged on the substrate, and the magnetic cover is packaged on the top of the packaging material and is magnetic.

Abstract: Systems and methods are provided for reading data from non-volatile storage devices and decoding the read data. A method may include obtaining a unique identifier for a storage location to be read, retrieving from a memory an adjustment to read reference voltage (Vref) associated with the unique identifier, performing a read operation on the storage location using a read reference voltage adjusted by the adjustment to Vref, decoding data read from the storage location in a decoding process and updating the adjustment to Vref with decoding information generated during the decoding process.

Abstract: Systems, apparatus and methods are provided for providing an error correction code (ECC) architecture with flexible memory mapping. An apparatus may include an error correction code (ECC) engine, a multi-channel interface for one or more non-volatile storage devices, a memory including a plurality of memory units, a storage containing a plurality of mapping entries to indicate allocation status of the plurality of memory units and a memory mapping manager. The plurality of memory units may be coupled to the ECC engine and the multi-channel interface. The memory mapping manager may be configured to control allocation of the plurality of memory units and set allocation status in the plurality of mapping entries.

Abstract: The present disclosure relates to methods and systems for evaluating a storage medium. The method may include receiving, via a user interface of a host, a user request to evaluate a storage medium coupled to a first controller. The method may also include determining whether there is a first binding history table associated with the storage medium stored in the host. In response to a determination that there is no first binding history table stored in the host, the method may include retrieving a binding history table from the storage medium via the first controller and determining the storage medium as a second-hand storage medium if there is at least one second controller different from the first controller in the binding history table.

Abstract: Systems, apparatus and methods are provided for providing an error correction code (ECC) architecture with flexible memory mapping. An apparatus may include an error correction code (ECC) engine, a multi-channel interface for one or more non-volatile storage devices, a memory including a plurality of memory units, a storage containing a plurality of mapping entries to indicate allocation status of the plurality of memory units and a memory mapping manager. The plurality of memory units may be coupled to the ECC engine and the multi-channel interface. The memory mapping manager may be configured to control allocation of the plurality of memory units and set allocation status in the plurality of mapping entries.

Abstract: Systems, apparatus and methods are provided for electrical mirroring implemented by a storage controller in a non-volatile storage system. In one embodiment, a non-volatile storage system may comprise a plurality of non-volatile storage devices and a storage controller. The storage controller may be configured to perform an electrical mirroring configuration process comprising: determining a system topology of the non-volatile storage system and which targets are in mirrored non-volatile storage devices and setting respective register bits in the storage controller for all targets in all mirrored non-volatile storage devices of the plurality of non-volatile storage devices.

Abstract: Systems, apparatus and methods are provided for multi-drop multi-load NAND interface topology where a number of NAND flash devices share a common data bus with a NAND controller. A method for controlling on-die termination in a non-volatile storage device may comprise receiving a chip enable signal on a chip enable signal line from a controller, receiving an on-die termination (ODT) command on a data bus from the controller while the chip enable signal is on, decoding the on-die termination command and applying termination resistor (RTT) settings in the ODT command to a selected non-volatile storage unit at the non-volatile storage device to enable ODT for the selected non-volatile storage unit.

Abstract: The present disclosure discloses a multilayer circuit board comprising a plurality of metal layers, a blind via and/or a buried via, the multilayer circuit board is capable of transmitting signal between the different metal layers. The blind via has a pad on a non-opening side of the blind via. An upper or lower layer metal layer on the non-opening side of the blind via adjacent to the blind via has a first hole which is located in a position corresponding to the pad on the non-opening side of the blind via in a depth direction of the blind via; and/or an upper and/or lower layer adjacent to the buried via has a second hole which is located in a position corresponding to the pad of an upper and/or lower orifice of the buried via in a depth direction of the buried via.

Abstract: The present disclosure relates to a relaxation oscillator, an integrated circuit and an electronic apparatus, the relaxation oscillator comprising a first signal generation module and an oscillation module configured to output a first oscillation signal and a second oscillation signal, the first oscillation signal and the second oscillation signal being opposite in phase, the oscillation module comprising a first switch, a second switch, a capacitor, and a comparison unit. The oscillation module according to the disclosed embodiment using a floating amplifier to implement a comparator, where in a pre-charging stage, the first switch and the second switch are turned on to charge the capacitor, and a common mode of the first oscillation signal and the second oscillation signal is determined; in a comparing stage, the first switch and the second switch are turned off to output the oscillation signal.