Abstract: The present disclosure relates to a relaxation oscillator, an integrated circuit and an electronic apparatus, the relaxation oscillator comprising a first signal generation module and an oscillation module configured to output a first oscillation signal and a second oscillation signal, the first oscillation signal and the second oscillation signal being opposite in phase, the oscillation module comprising a first switch, a second switch, a capacitor, and a comparison unit. The oscillation module according to the disclosed embodiment using a floating amplifier to implement a comparator, where in a pre-charging stage, the first switch and the second switch are turned on to charge the capacitor, and a common mode of the first oscillation signal and the second oscillation signal is determined; in a comparing stage, the first switch and the second switch are turned off to output the oscillation signal.

Abstract: Systems and methods are provided for decoding data read from non-volatile storage devices. A method may comprise receiving a chunk of data read from a physical location of a non-volatile storage device and searching a memory for soft information associated with the physical location using a unique identifier associated with the physical location. The soft information may be generated from one or more previous decoding processes on previous data from the physical location. The method may further comprise retrieving the soft information identified by the unique identifier associated with the physical location from the memory, decoding the chunk of data with the soft information indicating reliability of bits in the chunk of data and updating the soft information with decoding information generated during the decoding.

Abstract: The present disclosure relates to methods and systems for evaluating a storage medium. The method may include receiving, via a user interface of a host, a user request to evaluate a storage medium coupled to a first controller. The method may also include determining whether there is a first binding history table associated with the storage medium stored in the host. In response to a determination that there is no first binding history table stored in the host, the method may include retrieving a binding history table from the storage medium via the first controller and determining the storage medium as a second-hand storage medium if there is at least one second controller different from the first controller in the binding history table.

Abstract: Systems and methods are provided for concatenated error-correcting coding. An apparatus may include a Low-Density Parity-Check (LDPC) decoder configured to perform an iterative LDPC decoding process on bits of an LDPC codeword, a Bose—Chaudhuri—Hocquenghem (BCH) decoder coupled to the LDPC decoder and a BCH scheduler coupled to the LDPC decoder and the BCH decoder. The LDPC codeword may be generated by LDPC encoding a Bose—Chaudhuri—Hocquenghem (BCH) codeword and the BCH codeword may be generated by BCH encoding a data unit. The BCH scheduler may be configured to determine whether a triggering condition for the BCH decoder is met after each iteration of the iterative LDPC decoding process and activate the BCH decoder to operate on an intermediate decoding result of the LDPC decoder if the triggering condition for the BCH decoder is met.

Abstract: Systems, apparatus and methods are provided for loopback testing techniques for memory controllers. A memory controller that may comprise loopback testing circuitry that may comprise a first multiplexer having a first input coupled to an output of an input buffer and a second input coupled to a first data output from the memory controller, an inverter coupled to the output of the input buffer, and a second multiplexer having a first input coupled to an output of the inverter and a second input coupled to a second data output from the memory controller.

Abstract: Systems and methods are provided for decoding data read from non-volatile storage devices. A method that may include decoding a first codeword read from a storage location of a non-volatile storage device using a first decoder without soft information, determining that the first decoder has failed to decode the first codeword, decoding the first codeword using a second decoder without soft information, determining that the second decoder has succeeded in decoding the first codeword, generating soft information associated with the storage location using decoding information generated by the second decoder and decoding a subsequent codeword from the storage location using the soft information associated with the storage location. The second decoder may be more powerful than the first decoder.

Abstract: Systems, apparatus and methods are provided for logical-to-physical (L2P) address translation. A method may comprise receiving a request for a first logical data address (LDA), and calculating a first translation data unit (TDU) index for a first TDU. The first TDU may contain a L2P entry for the first LDA. The method may further comprise searching a cache of lookup directory entries of recently accessed TDUs using the first TDU index, determining that there is a cache miss, generating and storing an outstanding request for the lookup directory entry for the first TDU in a miss buffer, retrieving the lookup directory entry for the first TDU from an in-memory lookup directory, determining that the lookup directory entry for the first TDU is not valid, reserve a TDU space for the first TDU in a memory and generating a load request for the first TDU.

Abstract: The present disclosure relates to an emulation test system for flash translation layer and a method thereof, the system comprising a network block device, a virtual hardware accelerator, a flash translation layer module, and a virtual flash memory based on the network block device, wherein the network block device is configured to receive and forward test information, the test information including a read instruction and/or a write instruction and data to be written; the virtual hardware accelerator is configured to allocate the test information to each thread of the virtual hardware accelerator and perform virtual hardware acceleration on the flash translation layer module; and the flash translation layer module is configured to operate the virtual flash memory based on the test information to obtain an operation result.

Abstract: Systems and methods are provided for performing error recovery using LLRs generated from multi-read operations. A method may comprise selecting a set of decoding factors for a multi-read operation to read a non-volatile storage device multiple times. The set of decoding factors may include a total number of reads, an aggregation mode for aggregating read results of multiple reads, and whether the read results include soft data. The method may further comprise issuing a command to the non-volatile storage device to read user data according to the set of decoding factors, generating a plurality of Log-Likelihood Ratio (LLR) values using a mapping engine from a pre-selected set of LLR value magnitudes based on the set of decoding factors, obtaining an aggregated read result in accordance with the aggregation mode and obtaining an LLR value from the plurality of LLR values using the aggregated read result as an index.

Abstract: Systems and methods are provided for tracking read reference voltages used for reading data in a non-volatile storage device. A method may comprise collecting pre-decoding state information for a read reference voltage by reading data stored in a non-volatile storage device using the read reference voltage, collecting post-decoding state information for the read reference voltage after decoding the data, generating a comparison of probability of state errors for the read reference voltage based on the pre-decoding state information and post-decoding state information, obtaining an adjustment amount to the read reference voltage based on the comparison of probability of state errors; and adjusting the read reference voltage by applying the adjustment amount to the read reference voltage to obtain an adjusted read reference voltage.

Abstract: A reading method for solid-state disk returns data and/or information depending on state information. A data unit stored in the solid-state disk comprises metadata and a plurality of sectors including at least two sectors of user data, the metadata comprising a sector state set indicating state information of each of the sectors in the data unit, and the state information comprising a valid state and an invalid state. In response to receiving a read command from a host to read at least one of the sectors in the data unit, the solid-state disk returns actual data to the host for one or more of the sectors in the valid state, and returns information indicating a read error to the host for one or more of the sectors in the invalid state, according to the sector state set stored in the metadata of the data unit.

Abstract: A method for data processing, comprising updating intermediate storage information according to data to be processed and address information of the data to be processed in a first storage space, until the intermediate storage information has reached a preset size; and performing, in the first storage space, an operation corresponding to the data to be processed using the intermediate storage information, when the intermediate storage information reaches the preset size. By the above method, the computing cost for performing an operation corresponding to the data to be processed in the first storage space can be reduced, the efficiency in performing the corresponding operation can be improved, and with intermediate storage information adapted to the first storage spaces of different sizes, the number of operations on the first storage spaces can be reduced.

Abstract: Systems, apparatus and methods are provided for performing program operations in a non-volatile storage system. In one embodiment, there is provided a method that may comprise categorizing active storage blocks of a non-volatile storage device into a robust group and a less-robust group based on a number of factors including page error count, program time and number of Program/Erase (P/E) cycles; determining that a cache program operation needs to be performed; selecting a first storage block from the robust group to perform the cache program operation; determining that a regular program operation needs to be performed; and selecting a second storage block from the less-robust group to perform the regular program operation.

Abstract: Apparatus and methods are provided for managing operations of a semiconductor chip. In an exemplary embodiment, there is provided a semiconductor chip that may comprise a temperature sensor, a thermal heater, a processor and thermal control logic. The thermal control logic may be configured to: determine that a first temperature read-out from the temperature sensor reaches a first temperature threshold value, turn on the thermal heater, determine that a second temperature read-out from the temperature sensor reaches a second temperature threshold value that is lower than the first temperature threshold value, suspend functions of the processor, determine that a third temperature read-out from the temperature sensor reaches the first temperature threshold value, resume the functions of the processor, determine that a fourth temperature read-out from the temperature sensor reaches a third temperature threshold value that is higher than the first temperature threshold value and turn off the thermal heater.

Abstract: Systems, apparatus and methods are provided for using a partial logical-to-physical (L2P) address translation table for multiple namespaces to perform address translation. An exemplary embodiment may provide a method comprising: receiving a request for a first logical data address (LDA) that belongs to a first namespace (NS); searching the first NS in an entry location table (ELT) for all namespaces whose L2P entries always reside in memory; determining that the first NS is not in the ELT; searching a cache of lookup directory entries of recently accessed translation data units (TDUs) for a first TDU containing a L2P entry for the first LDA; determining that there is a cache miss; retrieving the lookup directory entry for the first TDU from an in-memory lookup directory and determining that it is not valid; reserving a TDU space for the first TDU; and generating a load request for the first TDU.

Abstract: Systems, apparatus and methods are provided for providing fast non-volatile storage access with ultra-low latency. A method may comprise dividing a user data unit into a plurality of data chunks, generating a plurality of error correction code (ECC) codewords and at least one ECC parity block and transmitting the plurality of ECC codewords and the at least one ECC parity block to a plurality of channels of the non-volatile storage device for each of the plurality of ECC codewords and the at least one ECC parity block to be stored in different channels of the plurality of channels.

Abstract: Apparatus and methods are provided for managing voltage drops on a semiconductor chip. One exemplary embodiment according to the present disclosure may provide a method for managing voltage drops in a semiconductor chip. The method may comprise monitoring power supply voltages for different voltage domains in the semiconductor chip by a voltage drop detection circuit, determining that a voltage drop event has occurred based on voltage information and duration information associated with the voltage drop event reported from the voltage drop detection circuit, generating diagnostic information that includes whether the voltage drop event is an external event or an internal event determined based on the voltage information and timing information reported from the voltage drop detection circuit, and taking an action based on the diagnosis information.

Abstract: A memory system is disclosed in the present disclosure. The memory system may include at least one first type of memory configured on at least one first rank and to operate at a first frequency, and at least one second type of memory configured on at least one second rank and to operate at a second frequency. The memory system may also include a physical block (PHY) configured to generate a first clock at the first frequency and a second clock at the second frequency.

Abstract: A method and apparatus for determining a reference voltage id disclosed. The method may include: reading data from a first flash memory page by using different reference voltages, and taking, as a first target reference voltage, one of the different reference voltages at which the first number of erroneous bits of the data that is read reaches a converegence value. The first flash memory page is any one of multiple flash memory pages of a flash memory block to be tested. The method may include adjusting the first target reference voltage to obtain second target reference voltages; and reading data from the flash memory pages by using the second target referece voltages, and taking, as a target reference voltage, one of the second target reference voltages at which the second number of erroneous bits of the data that is read is the smallest.

Abstract: An oscillator circuit includes an integrator, a comparator, an edge triggered flip-flop, and first and second capacitors. The edge triggered flip-flop has an input terminal coupled to an output terminal of the comparator and is configured to output first and second signals which are mutually exclusive, and to flip the signals when detecting a rising or falling edge output by the comparator such that: when the first signal is at a designated level, the first capacitor is charged and the second capacitor is discharged, and a terminal of the first capacitor is coupled to an input terminal of the integrator; and when the second signal is at a designated level, the second capacitor is charged and the first capacitor is discharged and a terminal of the second capacitor is coupled to the input terminal of the integrator.