Abstract: Semiconductor device structures and methods for manufacturing the same are provided. The semiconductor device structure includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a first electrode, a second electrode, a gate structure and a temperature sensitive component. The first nitride semiconductor layer is disposed on the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer and has a bandgap greater than that of the first nitride semiconductor layer. The first electrode, the second electrode and the gate structure are disposed on the second nitride semiconductor layer. The temperature sensitive component is disposed external to a region between the gate structure and the first electrode along a first direction in parallel to an interface of the first nitride semiconductor layer and the second nitride semiconductor layer.

Abstract: A semiconductor device and a method for manufacturing the same are provided in this disclosure. The semiconductor device includes a semiconductor heterostructure layer. The semiconductor heterostructure layer includes alternating first semiconductor material layers and second semiconductor material layers. Two-dimensional electron gas (2DEG) may be generated between each first semiconductor material layer and adjacent second semiconductor material layer. A conductive structure, including a plurality of conductive fingers extends from a surface of the semiconductor heterostructure layer into the semiconductor heterostructure layer. The plurality of conductive fingers are arranged in a direction substantially parallel to the surface. The lengths of the plurality of conductive fingers progressively increase in that direction so that an end portion of each conductive finger is respectively positioned in a different second semiconductor material layer and is not in contact with the 2DEG.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method thereof. The semiconductor device includes a semiconductor heterostructure layer and a conductive structure. The semiconductor heterostructure layer includes alternating first semiconductor material layers and second semiconductor material layers. 2DHGs may be generated between each first semiconductor material layer and adjacent second semiconductor material layer. The conductive structure includes a plurality of conductive fingers extending from a surface of the semiconductor heterostructure layer into the semiconductor heterostructure layer. The plurality of conductive fingers are arranged in a direction substantially parallel to the surface. The lengths of the plurality of conductive fingers progressively increase in that direction, so that an end portion of each conductive finger is respectively positioned in a different second semiconductor material layer and is not in contact with the 2DHG.

Abstract: A semiconductor device structure and a method for manufacturing the same are provided. The semiconductor device structure includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a third nitride semiconductor layer, a first electrode and a second electrode. The first nitride semiconductor layer is disposed on the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer. The third nitride semiconductor layer is disposed on the second nitride semiconductor layer. The first electrode is disposed on the second nitride semiconductor layer and spaced apart from the third nitride semiconductor layer. The second electrode covers an upper surface of the third nitride semiconductor layer and is in direct contact with the first nitride semiconductor layer.

Abstract: An electronic device includes a substrate, a transistor and a doped well. The substrate includes a first region and a second region different from the first region. The transistor is disposed on the first region of the substrate. The transistor includes a first nitride semiconductor layer disposed on the substrate, and a second nitride semiconductor layer disposed on the first nitride semiconductor layer. The second nitride semiconductor layer has a bandgap greater than that of the first nitride semiconductor layer. The doped well is disposed in the second region.

Abstract: The electronic circuits and semiconductor device having the same are provided. The electronic circuit includes: a first transistor including a first electrode coupled with an input voltage; a second transistor including a first electrode coupled with a second electrode of the first transistor; a first capacitor coupled between the first transistor and the second transistor; a first diode including a first terminal coupled with the first electrode of the first transistor; a second diode including a first terminal coupled with a second terminal of the first diode and a second terminal coupled with a second electrode of the second transistor; a second capacitor coupled between the first transistor and the first diode; and a third capacitor coupled between the first diode and the second transistor.

Abstract: The present disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a substrate, a group III-V layer disposed on the substrate, a dielectric layer disposed on the group III-V layer, and an inclined sidewall extending from the dielectric layer to the substrate. Wherein the substrate comprising a relative rough surface opposite the inclined sidewall.

Abstract: The HEMT includes a channel layer, a barrier layer, a drain, and a gate conductor. The barrier layer is disposed on the channel layer. The drain is disposed on the barrier layer. The gate conductor is disposed on the barrier layer. The barrier layer comprises a doped semiconductor region extending from a top surface to a bottom surface of the barrier layer and located between the drain and the gate conductor.

Abstract: Some embodiments of the disclosure provide a semiconductor device. The semiconductor device includes: a doped substrate; a barrier layer, disposed on the doped substrate; a channel layer, disposed between the doped substrate and the barrier layer; and a doped semiconductor structure, disposed in the doped substrate, where a band gap of the barrier layer is greater than a band gap of the channel layer, and the doped substrate and the doped semiconductor structure have different polarities.

Abstract: A semiconductor device includes a substrate, a channel layer, a barrier layer, a gate, a strained layer and a passivation layer. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The gate is disposed on the barrier layer. The strained layer is disposed on the barrier layer. The passivation layer covers the gate and the strained layer. The material of the passivation layer differs from that of the strained layer.

Abstract: A semiconductor apparatus includes a channel layer, a barrier layer, a source contact and a drain contact, a first doped group III-V semiconductor, a group III-V semiconductor, and a second doped group III-V semiconductor. The barrier layer is disposed on the channel layer. The source contact and the drain contact are disposed on the channel layer. The first doped group III-V semiconductor is disposed on the barrier layer. The group III-V semiconductor is disposed on the first doped group III-V semiconductor and between the source contact and the drain contact. The second doped group III-V semiconductor is disposed on the group III-V semiconductor and between the source contact and the drain contact. The group III-V semiconductor has a central region covered by the second doped group III-V semiconductor and a peripheral region free from coverage by the second doped group III-V semiconductor.

Abstract: A semiconductor device includes a channel layer, a barrier layer, source contact and a drain contact, a doped group III-V layer, and a gate electrode. The barrier layer is positioned above the channel layer. The source contact and the drain contact are positioned above the barrier layer. The doped group III-V layer is positioned above the barrier layer and between the first drain contact and the first source contact. The first doped group III-V layer has a first non-vertical sidewall and a second non-vertical sidewall. The gate electrode is positioned above the doped group III-V layer and has a third non-vertical sidewall and a fourth non-vertical sidewall. A horizontal distance from the first non-vertical sidewall to the third non-vertical sidewall is different than a horizontal distance from the second non-vertical sidewall to the fourth non-vertical sidewall.

Abstract: The present disclosure provides an electrostatic protection circuit and an electronic device. The electrostatic protection circuit is connected to a first end point and a second end point of a power device. The electrostatic protection circuit is configured to allow bilateral electrostatic protection between the first end point and the second end point of the power device. The power device includes a transverse high-electron-mobility transistor (HEMT).

Abstract: The application relates to a device and method for measuring a high electron mobility transistor. The device provided includes a controller, a protection circuit, a load circuit and a switching circuit electrically connected between the load circuit and the protection circuit. The controller is configured to provide a first control signal having a first value to a semiconductor component at a first time point and provide a second control signal having a second value to the switching circuit at a second time point. The semiconductor component is turned on by the first value of the first control signal, and the switching circuit is turned on by the second value of the second control signal. The second time point is later than the first time point.

Abstract: Embodiments of this application disclose a semiconductor device and a manufacturing method thereof. The semiconductor device includes a substrate, a first nitride semiconductor layer disposed on the substrate and having a first bandgap, and a second nitride semiconductor layer disposed on the first nitride semiconductor layer and having a second bandgap. The second bandgap is larger than the first bandgap. The semiconductor device further includes a gate contact disposed over the second nitride semiconductor layer and a first field plate disposed over the gate contact. The first field plate has a first surface facing the substrate, a second surface facing the substrate, and a protruded portion. The protruded portion has a bottom surface facing the substrate. The bottom surface is located between the first surface and the second surface.

Abstract: A testing circuit includes a first circuit and a second circuit. The first circuit and second circuit have a first capacitor and a second capacitor. The first circuit is connected to a first transistor. The second circuit is connected to a second transistor. A first inductor has a first terminal connected to an input of the testing circuit and a second terminal connected to a source of the second transistor. A first diode has an anode connected to ground and a cathode connected to the second terminal of the first inductor. The second capacitor has a first terminal connected to a drain of the second transistor and a second terminal connected to ground. The first capacitor has a first terminal connected to the input of the testing circuit and a second terminal connected to ground.

Abstract: The present disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a substrate, a channel layer disposed on the substrate, and a barrier layer disposed on the channel layer. The semiconductor device further includes a dielectric layer disposed on the barrier layer and defining a first recess exposing a portion of the barrier layer. The semiconductor device further includes a first spacer disposed within the first recess, wherein the first spacer comprises a surface laterally connecting the dielectric layer to the barrier layer.

Abstract: An electronic device includes a first group III nitride transistor and an over current protection circuit (OCP). The OCP circuit includes an input device and a detection device. The input device is configured to receive a control signal and to generate a first voltage to a gate of the first group III nitride transistor. The detection device is configured to generate an output signal having a first logical value if a current at a drain of the first group III nitride transistor is less than a predetermined value and to generate the output signal having a second logical value if the current at the drain of the first group III nitride transistor is equal to or greater than the predetermined value, wherein the first logical value is different from the second logical value.

Abstract: The present disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a III-V material layer, a first gate, a second gate, and a first passivation layer. The first gate and the second gate are on the III-V material layer. The first passivation layer is on the first gate. A first activation ratio of an element in the first gate is different from a second activation ratio of the element in the second gate.

Abstract: An electronic device includes a first group III nitride transistor and an electrostatic discharge (ESD) protection circuit. The ESD protection circuit includes a diode and a second transistor. The diode has an anode electrically connected to a gate of the first group III nitride transistor. The second transistor has a drain electrically connected to the gate of the first group III nitride transistor, a gate electrically connected to a cathode of the diode and a source electrically connected to a source of the first group III nitride transistor.