Abstract: The present disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a III-nitride layer, a gate, a connection structure, and a gate bus. The gate is disposed over the III-nitride layer. The connection structure is disposed over the gate. The gate bus extends substantially in parallel to the gate and disposed over the connection structure from a top view perspective. The gate bus is electrically connected to the gate through the connection structure.

Abstract: The semiconductor device structure includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a first electrode, a second electrode, a gate structure and a temperature sensitive component. The first nitride semiconductor layer is disposed on the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer and has a bandgap greater than that of the first nitride semiconductor layer. The first electrode is disposed on the second nitride semiconductor layer. The second electrode is disposed on the second nitride semiconductor layer. The gate structure is disposed on the second nitride semiconductor layer and between the first electrode and the second electrode. The temperature sensitive component is disposed external to a region between the gate structure and the first electrode along a first direction in parallel to an interface of the first nitride semiconductor layer and the second nitride semiconductor layer.

Abstract: An apparatus for measuring dynamic on-resistance of a device under test (DUT) is provided. The apparatus comprises a testing interface configured for coupling between the DUT and a measuring equipment; a first measuring circuit configured for sensing a drain-source voltage of the DUT and generating a first measuring signal proportional to the drain-source voltage; a current sensing circuit configured for sensing a drain current flowing from a drain to a source of the DUT and generating a current sensing signal; a second measuring circuit configured for receiving the current sensing signal and generating a second measuring signal proportional to the drain current; a first clamping circuit configured for eliminating overshoots in the first measuring signal; a second clamping circuit configured for eliminating overshoots in the second measuring signal. As the overshoot in the measuring voltage signals can be eliminated, the time required for the measuring signal to settle is shortened.

Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a first nitride semiconductor layer, a second nitride semiconductor layer, a gate structure, and a field plate. The second nitride semiconductor layer is formed on a first surface of the first nitride semiconductor layer. The gate structure is disposed on the second nitride semiconductor layer. The field plate includes a first portion and a second portion connected to the first portion. The first portion has a first surface substantially in parallel to the first surface of the first nitride semiconductor layer, and a second surface adjacent to the first surface of the first portion. The first surface of the first portion of the field plate and the second surface of the first portion of the field plate define a first angle of about 90°.

Abstract: A semiconductor structure includes a first nitride semiconductor layer; a second nitride semiconductor layer and a first conductive structure. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer. The first conductive structure is disposed on the second nitride semiconductor layer. The first conductive structure functions as one of a drain and a source of a transistor and one of an anode and a cathode of a diode.

Abstract: A semiconductor device includes a doped substrate, a barrier layer, a channel layer, and a doped semiconductor structure. The barrier layer is disposed on the doped substrate. The channel layer is disposed between the doped substrate and the barrier layer, in which a bandgap of the barrier layer is greater than a bandgap of the channel layer. The doped semiconductor structure is embedded in the doped substrate and at a position lower than the channel layer, in which the doped substrate and the doped semiconductor structure have different polarities, so as to form a diode therebetween.

Abstract: A semiconductor device includes a doped substrate, a barrier layer, a channel layer, a doped semiconductor structure, and the conductive structure. The barrier layer is disposed on the doped substrate. The channel layer is disposed between the doped substrate and the barrier layer, in which a bandgap of the barrier layer is greater than a bandgap of the channel layer. The doped semiconductor structure is embedded in the doped substrate, in which the doped substrate and the doped semiconductor structure have different polarities, so as to form a diode therebetween. The conductive structure is disposed over the doped substrate and makes contact with the doped semiconductor structure, in which the conductive structure extends from the doped semiconductor structure to a position higher than the channel layer and the barrier layer.

Abstract: Some embodiments of the disclosure provide a semiconductor device. The semiconductor device comprises: a substrate; a first nitride semiconductor layer on the substrate; a second nitride semiconductor layer on the first nitride semiconductor layer and having a band gap greater than a band gap of the first nitride semiconductor layer; a group III-V dielectric layer disposed on the second nitride semiconductor layer; a gate electrode disposed on the second nitride semiconductor layer; and a first passivation layer disposed on the group III-V dielectric layer, wherein the group III-V dielectric layer is separated from the gate electrode by the first passivation layer.

Abstract: A semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a substrate; a first nitride semiconductor layer disposed on the substrate; a second nitride semiconductor layer disposed on the first nitride semiconductor layer and having a bandgap greater than that of the first nitride semiconductor layer, the second nitride semiconductor layer forming a first recess and a second recess; and an electrode disposed on the second nitride semiconductor layer and comprising an element; wherein the electrode is disposed in the first recess and the second recess.

Abstract: Semiconductor device structures and methods for manufacturing the same are provided. The semiconductor device structure includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a gate structure and a conductive layer. The substrate has a first surface. The first nitride semiconductor layer is disposed on the first surface of the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer. The gate structure is disposed on the second nitride semiconductor layer. The conductive layer is disposed on the second nitride semiconductor layer. The conductive layer has a first length extending in a first direction substantially parallel to the first surface of the substrate, a second length extending in a second direction substantially perpendicular to the first direction—from a cross section view perspective—wherein the second length is greater than the first length.

Abstract: A semiconductor device and a method for manufacturing the same are provided in this disclosure. The semiconductor device includes a semiconductor heterostructure layer. The semiconductor heterostructure layer includes alternating first semiconductor material layers and second semiconductor material layers. Two-dimensional hole gas (2DHG) may be generated between each first semiconductor material layer and adjacent second semiconductor material layer. A conductive structure, including a plurality of conductive fingers extends from a surface of the semiconductor heterostructure layer into the semiconductor heterostructure layer. The plurality of conductive fingers are arranged in a direction substantially parallel to the surface. The lengths of the plurality of conductive fingers progressively increase in that direction so that an end portion of each conductive finger is respectively positioned in a different first semiconductor material layer and is in contact with the 2DHG.

Abstract: Some embodiments of the present disclosure provide a semiconductor device including a channel layer, a barrier layer, a p-type doped III-V layer, a gate, a drain, and a doped semiconductor layer. The barrier layer is disposed on the channel layer. The p-type doped III-V layer is disposed on the barrier layer. The gate is disposed on the p-type doped III-V layer. The drain is disposed on the barrier layer. The doped semiconductor layer is disposed on the barrier layer and is covered by the drain. The drain has a first portion located between the p-type doped III-V layer and an entirety of the doped semiconductor layer.

Abstract: The present disclosure relates to a semiconductor device and a fabrication method thereof. The semiconductor device includes a substrate, a first nitride semiconductor layer on the substrate and a second nitride semiconductor layer on the first nitride semiconductor layer. The second nitride semiconductor layer has a first area and a second area, and the second nitride semiconductor layer has single crystals. The semiconductor device includes an electrode in contact with the first area. A first concentration of Aluminum (Al) of the first area is less than a second concentration of Al of the second area, and the single crystals in the first area take over a crystal structure of the first nitride semiconductor layer.

Abstract: A semiconductor device structure includes a substrate, a channel layer, a barrier layer and a doped group III-V layer. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The doped group III-V layer is disposed on the barrier layer. The doped group III-V layer includes a first portion and a second portion. The first portion has a first concentration of a first element. The second portion is adjacent to the first portion and has a second concentration of the first element. The gate structure is disposed on the first portion of the doped group III-V layer. The first concentration of the first element is different from the second concentration of the first element.

Abstract: The present disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a III-V material layer and a gate structure. The gate structure includes a first portion and a second portion on the first portion. The first portion is on the III-V material layer. The first portion has a first surface and a second surface opposite to the first surface and adjacent to the III-V material layer. A length of the second surface of the first portion of the gate structure is less than a length of the first surface of the first portion of the gate structure. A length of the second portion of the gate structure is less than the length of the first portion of the gate structure.

Abstract: The semiconductor device structure includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a first electrode, a second electrode, a gate structure and a temperature sensitive component. The first nitride semiconductor layer is disposed on the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer and has a bandgap greater than that of the first nitride semiconductor layer. The first electrode is disposed on the second nitride semiconductor layer. The second electrode is disposed on the second nitride semiconductor layer. The gate structure is disposed on the second nitride semiconductor layer and between the first electrode and the second electrode. The temperature sensitive component is disposed external to a region between the gate structure and the first electrode along a first direction in parallel to an interface of the first nitride semiconductor layer and the second nitride semiconductor layer.

Abstract: The present invention relates to a semiconductor device having an improved gate leakage current. The semiconductor device includes: a substrate; a first nitride semiconductor layer, positioned above the substrate; a second nitride semiconductor layer, positioned above the first nitride semiconductor layer and having an energy band gap greater than that of the first nitride semiconductor layer; a source contact and a drain contact, positioned above the second nitride semiconductor layer; a doped third nitride semiconductor layer, positioned above the second nitride semiconductor layer and between the drain contact and the source contact; and a gate electrode, positioned above the doped third nitride semiconductor layer, where the doped third nitride semiconductor layer has at least one protrusion extending along a direction substantially parallel to an interface between the first nitride semiconductor layer and the second nitride semiconductor layer, thereby improving the gate leakage current phenomenon.

Abstract: Semiconductor device structures and methods for manufacturing the same are provided. The semiconductor device structure includes a substrate, a first layer and a second layer. The first layer is disposed on and in contact with the substrate. The first layer includes AlX1Ga(1-X1)N, wherein 0.5?X1<1. The second layer is disposed on and in contact with the first layer. The second layer includes Al, Ga and N.

Abstract: A semiconductor device and a clamping circuit including a substrate; a first semiconductor layer, arranged on the substrate and composed of a III-nitride semiconductor material; a second semiconductor layer, arranged on the first semiconductor layer and composed of a III-nitride semiconductor material; a power transistor structure, including a gate structure, a drain structure and a source structure arranged on the second semiconductor layer; the first transistor structures, arranged on the second semiconductor layer; and the second transistor structures, arranged on the second semiconductor layer in series. One end of the first transistor structures and one end of the second transistor structures are jointly electrically connected to the drain structure of the power transistor structure, and the other end of the first transistor structures and the other end of the second transistor structures are jointly electrically connected to the source structure of the power transistor structure.

Abstract: A semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a substrate; a first nitride semiconductor layer disposed on the substrate; a second nitride semiconductor layer disposed on the first nitride semiconductor layer and having a bandgap greater than that of the first nitride semiconductor layer, the second nitride semiconductor layer forming a first recess and a second recess; and an electrode disposed on the second nitride semiconductor layer and comprising an element; wherein the electrode is disposed in the first recess and the second recess.