Abstract: A method of operating a deterministic microcontroller is disclosed in which the microcontroller is switchable to various contexts. A plurality of sets of hardware registers is provided. A corresponding plurality of hardware contexts for the microcontroller is provided by the plurality of sets of hardware registers. A context manager controls the selection of the hardware registers such that contexts are changed within one bus cycle and a plurality of hardware contexts are provided.

Abstract: A deterministic microcontroller includes a plurality of blocks of cache memories formed on the same integrated circuit as the microprocessor unit. A corresponding plurality of hardware contexts for the microcontroller is provided by the plurality of sets of hardware registers. A context manager controls the selection of the hardware registers such that contexts are changed within one bus cycle and a plurality of hardware contexts are provided. The deterministic microcontroller includes a configurable input/output interface that is programmable to handle any one of a plurality of interfaces that embedded applications might have, including communication protocols and bus interfaces, data acquisition from multiple sensors and actuators, and controls of various motors.

Abstract: A trace function method for microprocessors is provided. The method is operable with a microprocessor comprising an execution unit operable in one or a plurality of contexts. The method comprises: providing a memory coupled to the execution unit, utilizing the memory to store trace data during a trace operation; and providing hardware utilizable during a trace operation to assist in the trace operation.

Abstract: A method for preventing priority inversion in a processor system having an operating system operable in a plurality of contexts is provided. The method comprises: providing a plurality of context control registers with each context control register being associated with a corresponding one context for controlling execution of the context; providing a plurality of sets of hardware registers, each set corresponding to one context of the plurality of contexts; and utilizing the plurality of context control registers and said plurality of sets of hardware registers to prevent priority inversion.

Abstract: A deterministic microprocessor is disclosed in which a plurality of sets of hardware registers is provided. A corresponding plurality of hardware contexts for the microcontroller is provided by the plurality of sets of hardware registers.

Abstract: A method of providing a deterministic microcontroller includes a providing a plurality of blocks of cache memories formed on the same integrated circuit as a microprocessor unit.

Abstract: A method of operating a deterministic microcontroller is disclosed in which the microcontroller is switchable to various contexts. A plurality of sets of hardware registers is provided. A corresponding plurality of hardware contexts for the microcontroller is provided by the plurality of sets of hardware registers.

Abstract: A deterministic microcontroller includes a plurality of blocks of cache memories formed on the same integrated circuit as the microprocessor unit.

Abstract: A configurable application specific product with a configurable input/output interface is described. The illustrative embodiment of the invention includes a single microcontroller and a microprocessor having a configurable I/O interface that can be programmed to handle any one of a plurality of interfaces that embedded applications might have, including communication protocols and bus interfaces, data acquisition from multiple sensors and actuators, and controls of various motors.

Abstract: A configurable input/output interface is described that can be programmed to handle any one of a plurality of interfaces that embedded applications might have, including communication protocols and bus interfaces, data acquisition from multiple sensors and actuators, and controls of various motors.

Abstract: A deterministic microcontroller includes a plurality of blocks of cache memories formed on the same integrated circuit as the microprocessor unit. A corresponding plurality of hardware contexts for the microcontroller is provided by the plurality of sets of hardware registers. A context manager controls the selection of the hardware registers such that contexts are changed within one bus cycle and a plurality of hardware contexts are provided. The deterministic microcontroller includes a configurable input/output interface that is programmable to handle any one of a plurality of interfaces that embedded applications might have, including communication protocols and bus interfaces, data acquisition from multiple sensors and actuators, and controls of various motors.

Abstract: A method and apparatus for a fully programmable and configurable application specific integrated circuit (FPCA). Programmable I/O cells are programmed for selected electrical characteristics, including power and ground. The circuit contains a functional core for programming the circuit, programmable I/O leads to connect to the programmable I/O cells, and programming logic and control for programming the functional core and I/O cells. Certain leads double as programmable I/O leads and programming control leads, and are used to communicate with the programming logic and control and the I/O cells. A method of programming the FPCA comprises the steps of asserting the programming control signal; applying programming voltage and ground to a respective two designated I/O cells' leads; isolating a plurality of the I/O cells from the programming signal; and programming an FPGA array in addition to the isolated I/O cells of the circuit.