Abstract: A semiconductor optical amplifier for high-power operation includes a gain medium having a multilayer structure sequentially laid with a P-layer, an active layer, a N-layer from an upper portion to a lower portion in cross-section thereof. The gain medium is extendedly laid with a length L from a front facet to a back facet. The active layer includes multiple well layers formed by undoped semiconductor material and multiple barrier layers formed by n-doped semiconductor materials. Each well layer is sandwiched by a pair of barrier layers. The front facet is characterized by a first reflectance Rf and the back facet is characterized by a second reflectance Rb. The gain medium has a mirror loss ?m about 40-200 cm?1 given by: ?m=(½L)ln{1/(Rf×Rb)}.

Abstract: The present invention is directed to a communication signal tracking system comprising an optical receiver including one or more delay line interferometers (DLIs) configured to demultiplex incoming optical signals and a transimpedance amplifier configured to convert the incoming optical signals to incoming electrical signals. The communication signal tracking system further includes a control module configured to calculate a bit-error-rate (BER) of the incoming electrical signals before forward-error correction decoding, and use the BER as a parameter for optimizing settings of the one or more DLIs in one or more iterations in a control loop and generating a back-channel data.

Abstract: The present invention is directed to data communication system and methods. More specifically, various embodiments of the present invention provide a communication interface that is configured to transfer data at high bandwidth using PAM format(s) over optical communication networks. A feedback mechanism is provided for adjusting the transmission power levels. There are other embodiments as well.

Abstract: Receiver circuitry is disclosed that can take circuit branches offline to possibly adapt an offset value. In one embodiment, a circuit in a receiver has at least two branches. Each branch includes an adjustor to adjust the branch signal by an offset value. Selection circuitry takes one of the branches offline by selecting the output of that branch as an offline value, and by selecting the output of one or more of the other branches as a data decision value. The selection circuitry changes which branch is taken offline during the operation of the circuit. When a branch is taken offline, an offset value associated with that branch may be updated, if necessary.

Abstract: The present invention is directed to data communication system and methods. More specifically, various embodiments of the present invention provide a communication interface that is configured to transfer data at high bandwidth using PAM format(s) over optical communication networks. A feedback mechanism is provided for adjusting the transmission power levels. There are other embodiments as well.

Abstract: An extended-height DIMM for use in a memory system having slots designed to receive DIMMs that comply with a JEDEC standard that specifies a maximum height for the DIMM and a maximum number of devices allowed to reside on the DIMM. The DIMM comprises a PCB having an edge connector designed to mate with a memory system slot and a height which is greater than the maximum height specified in the applicable standard, a plurality of memory devices which exceeds the maximum number of devices specified in the applicable standard, and a memory buffer which operates as an interface between a host controller's data and command/address busses and the memory devices. This arrangement enables the extended-height DIMM to provide greater memory capacity than would a DIMM which complies with the maximum height and maximum number of devices limits.

Abstract: A memory interface device comprising an address match table. The address match table includes a content entry input and a plurality of hash functions numbered from 1 through N, where N is an integer greater than 1. The address match table includes a first table comprising a plurality of lists numbered from 1 through N, each hash function (i) corresponds to a list (i), where (i) is a number in a set from 1 through N, and a second table coupled to the first table, the second table comprising a plurality of entries, each of the entries point to a different entry within the second table or a null entry in the second table. The interface device includes an index from list N in the first table points to the second table.

Abstract: The present invention is directed to server systems and methods thereof. More specifically, embodiments of the present invention provides a memory controller within a server system, where the memory controller is disengageably connected to one or more processors, a plurality of volatile memory modules, and plurality of solid-state memory modules. This memory controller may be connected to other similarly configured memory controllers. The volatile and solid-state memory modules can be removed and/or replaced. There are other embodiments as well.

Abstract: The voltage regulator device has a wide band amplifier having an input reference voltage, Vref and an input feedback voltage, Vfbk. The device has a source follower coupled to the wide band amplifier, the source follower coupled to an output of the wide band amplifier. The device has a VDD source, a regulator output, and a current source coupled to the source follower and the VDD source. The device has a low frequency path comprising a first transistor. The first transistor has a first gate, a first source, and a first drain. The first source is coupled to the VDD source. The first gate is coupled to a slow node, and the first drain is coupled to the regulator output. The low frequency path comprises a RC network, which has a capacitor, a resistor, and the slow node configured between the resistor and the capacitor. The device has a high frequency path comprising a second transistor. The second transistor has a second gate, a second source, and a second drain. The second source is coupled to the VDD source.

Abstract: A method for operating a DRAM device. The method includes receiving in a memory buffer in a first memory module hosted by a computing system, a request for data stored in RAM of the first memory module from a host controller of the computing system. The method includes receiving with the memory buffer, the data associated with a RAM, in response to the request and formatting with the memory buffer, the data into a scrambled data in response to a pseudo-random process. The method includes initiating with the memory buffer, transfer of the scrambled data into an interface device.

Abstract: In an example, the present invention includes an integrated system on chip device. The device is configured on a single silicon substrate member. The device has a data input/output interface provided on the substrate member. The device has an input/output block provided on the substrate member and coupled to the data input/output interface. The device has a signal processing block provided on the substrate member and coupled to the input/output block. The device has a driver module provided on the substrate member and coupled to the signal processing block. In an example, the device has a driver interface provided on the substrate member and coupled to the driver module and configured to be coupled to a silicon photonics device. The device also has an interface configured to communicate between the silicon photonics device and the control block.

Abstract: A method for operating a memory system and a memory buffer device. The method includes receiving an external clock signal from a clock device of a CPU of a host computer to a buffer device, and receiving an ODT signal from the CPU to a command port of the buffer device. Buffer device provides the self-termination information internally to the common data bus by automatically detecting the read or write command on the common command bus and adjust the termination resistor array in a pre-determined value and timing fashion so that information can be read from or write to a data line of only one of the plurality of DIMM devices coupled together through a common data bus interface. All DIMM devices other than the DIMM device being read can be maintained in a termination state to prevent any signal from traversing to the common the common data bus interface.

Abstract: Apparatus to implement several high performance phase interpolators are disclosed. Some embodiments are directed to a full-wave integrating phase interpolation core comprising two pairs of in-phase and quadrature-phase current DACs arranged in a cascode architecture to drive an integrating capacitor and produce an interpolation voltage waveform. The current DACs are biased, weighted, and controlled by in-phase and quadrature-phase input clocks to yield an interpolation waveform that presents a phase value between the phases of the input clocks. Some embodiments deploying the interpolator core use feedback circuitry and reference voltages to adjust the common mode and amplitude of the interpolation voltage waveform to obtain both optimal performance and operation within the interpolator linear region or output compliance range.

Abstract: A DRAM refresh method used with a memory system organized into rows of memory cells, each of which has an associated data retention time, with the system arranged to refresh predefined blocks of memory cells simultaneously. For each block of memory cells that are to be refreshed simultaneously, the minimum data retention time for the memory cells in the block is determined. Then, an asymmetric refresh sequence is created which specifies the order in which the blocks of memory cells are refreshed, such that the blocks having the shortest minimum data retention times are refreshed more often than the blocks having longer minimum data retention times.

Abstract: A method for testing a memory device. The method can include coupling the memory device to a test apparatus and determining whether each of the memory cells in the memory device is within a first specification range. Each of the cells that fall outside of the first range can be identified. Each of the cells that meet the second specification range can be tested. The method can include selecting a tile associated with a highest number of cells that fall outside of the second range. A resource can then be used to repair each of the cells that fall outside of the second range for a tile associated with a fewer number of cells that fall outside of the second range such that a first number of tiles meets the first range and a second number of tiles meets the second range such that the first number the second number.

Abstract: A memory device comprising an interface device and a plurality of memory arrays. The interface device includes an address match table comprising at least a revised address corresponding to a spare memory location and a control module configured to determine address information from the address stream from an address command bus coupled to the host controller during a run time operation. The control module is configured to compare each address from the address stream and determine whether each address matches with a stored address in the address match table to identify a bad address and configured to replace the bad address with the revised address of the spare memory location. The device also has a plurality of memory arrays. Each of the memory arrays comprises a plurality of memory cells. The memory device has a spare group of memory cells comprising a plurality of spare memory cells. Each of the plurality of spare memory cells being addressable using the address match table.

Abstract: An integrated circuit memory interface device coupled to a dynamic random access memory device is provided. The device includes an address match table. The address match table includes a plurality of first addresses. Each of the first addresses is associated with a memory cell having a refresh characteristic outside of a specification for a DRAM device. The device has a plurality of second addresses. Each of the second addresses is associated with a refresh characteristic within a specification of the DRAM device and outside of a predetermined refresh characteristic range characterized to eliminate accesses to memory cells not meeting the predetermined refresh characteristic range.

Abstract: There is disclosed a memory system and method. The memory system may include a plurality of memory planes including two or more data memory areas, and a memory controller adapted to controlling reading, writing, and erasing of the plurality of memory planes. When any one of the data memory areas is occupied with one of a write operation and an erase operation, the controller may reconstruct data stored in the one occupied data memory area by reading parity information and data stored in the plurality of memory areas other than the one occupied data memory area.

Abstract: The present invention is directed to signal processing system and electrical circuits. More specifically, embodiments of the present invention provide a DLL system that provides phase correction by determining a system offset based on phase differences among the delay lines. The offset is used as a part of a feedback loop to provide phase corrections for the delay lines. There are other embodiments as well.

Abstract: The present invention is directed to communication system and methods. More specifically, various embodiments of the present invention provide a communication interface that is configured to transfer data at high bandwidth using PAM format(s) over optical communication networks. In certain embodiments, the communication interface is used by various devices within a spine-leaf network architecture, which allows large amount of data to be shared among servers.