Abstract: An integrated apparatus with optical/electrical interfaces and protocol converter on a single silicon substrate. The apparatus includes an optical module comprising one or more modulators respectively coupled with one or more laser devices for producing a first optical signal to an optical interface and one or more photodetectors for detecting a second optical signal from the optical interface to generate a current signal. Additionally, the apparatus includes a transmit lane module coupled between the optical module and an electrical interface to receive a first electric signal from the electrical interface and provide a framing protocol for driving the one or more modulators. Furthermore, the apparatus includes a receive lane module coupled between the optical module and the electrical interface to process the current signal to send a second electric signal to the electrical interface.

Abstract: The present invention is directed to data communication. In certain embodiments, the present invention provides switching mechanism for choosing between redundant communication links. Data received from a first set of communication links are processed to have alignment markers removed, and first figure of merit value is determined based on the data without alignment markers. Similarly, a second figure of merit value is determined for the data received from the second set of communication links. A switch selects between the first set of communication links and the second set of communication links based on their respective figure of merit values. Alignment markers are inserted into the data transmitted through the selected set of data links. There are other embodiments as well.

Abstract: The present invention is directed to data communication systems and techniques thereof. More specifically, embodiments of the present invention provide an FEC encoder that generates parity symbols that are embedded into FEC blocks. An FEC decoder determines whether to perform error correction based on the parity symbols. When performing error correction, the decoder selects a worst symbol from a segment of symbols, and the worst symbol is corrected. There are other embodiments as well.

Abstract: A receiver system that includes a clock and data recovery (CDR) system for aligning a local clock signal to an incoming data signal to extract correct timing information from the incoming data signal is provided. A timing error detector generates an output phase error signal representing the phase difference between the incoming data signal and the local clock signal. The timing error detector determines the phase difference according to recovered symbols and the difference between the recovered symbols and digital samples of the incoming data signal. The digital samples of the incoming data signal include intersymbol interference. The output timing information is suitable for aligning the local clock signal to the incoming data signal.

Abstract: A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal Fat the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.

Abstract: The present invention provides an integrated system-on-chip device. The device is configured on a single silicon substrate member. The device has a data input/output interface provided on the substrate member. The device has an input/output block provided on the substrate member and coupled to the data input/output interface. The device has a signal processing block provided on the substrate member and coupled to the input/output block. The device has a driver module provided on the substrate member and coupled to the signal processing block. The device further includes a driver interface and coupled to the driver module and configured to be coupled to a silicon photonics device. In an example, a control block is configured to receive and send instruction(s) in a digital format to the communication block and is configured to receive and send signals in an analog format to communicate with the silicon photonics device.

Abstract: A decoder performs forward error correction based on quasi-cyclic regular column-partition low density parity check codes. A method for designing the parity check matrix reduces the number of short-cycles of the matrix to increase performance. An adaptive quantization post-processing technique further improves performance by eliminating error floors associated with the decoding. A parallel decoder architecture performs iterative decoding using a parallel pipelined architecture.

Abstract: The present invention relates to telecommunication techniques and integrated circuit (IC) devices. More specifically, embodiments of the present invention provide an off-quadrature modulation system. Once an off-quadrature modulation position is determined, a ratio between DC power transfer amplitude and dither tone amplitude for a modulator is as a control loop target to stabilize off-quadrature modulation. DC power transfer amplitude is obtained by measuring and sampling the output of an optical modulator. Dither tone amplitude is obtained by measuring and sampling the modulator output and performing calculation using the optical modulator output values and corresponding dither tone values. There are other embodiments as well.

Abstract: A method and structure for compensation techniques in coherent optical receivers. The present invention provides a coherent optical receiver with an improved 8×8 adaptive MIMO (Multiple Input, Multiple Output) equalizer configured within a digital signal processor (DSP) to compensate the effects of transmitter I/Q skew in subcarrier multiplexing (SCM) schemes. The 8×8 MIMO equalizer can be configured such that each of the 8 outputs is electrically coupled to 3 of 8 inputs, wherein each of the input-output couplings is configured as a filter. The method includes compensating for impairments to the digital conversion of an optical input signal via the 8×8 MIMO equalizer following other signal processing steps, such as chromatic dispersion (CD)/polarization-mode dispersion (PMD) compensation, carrier recovery, timing synchronization, and cycle slip correction.

Abstract: An optical module processes first FEC (Forward Error Correction) encoded data produced by a first FEC encoder. The optical module has a second FEC encoder for further coding a subset of the first FEC encoded data to produce second FEC encoded data. The optical module also has an optical modulator for modulating, based on a combination of the second FEC encoded data and a remaining portion of the first FEC encoded data that is not further coded, an optical signal for transmission over an optical channel. The second FEC encoder is an encoder for an FEC code that has a bit-level trellis representation with a number of states in any section of the bit-level trellis representation being less than or equal to 64 states. In this manner, the second FEC encoder has relatively low complexity (e.g. relatively low transistor count) that can reduce power consumption for the optical module.

Abstract: The present invention is directed to data communication systems and techniques thereof. More specifically, embodiments of the present invention provide a retimer module that includes plurality of communication lanes for interfacing with a host system and a line system. The retimer module includes a link monitor and cross point sections. The retimer also includes a management interface module. There are other embodiments as well.

Abstract: A receiver applies a calibration method to compensate for skew between input channels. The receiver skew is estimated by observing the coefficients of an adaptive equalizer which adjusts the coefficients based on time-varying properties of the multi-channel input signal. The receiver skew is compensated by programming the phase of the sampling clocks for the different channels. Furthermore, during real-time operation of the receiver, channel diagnostics is performed to automatically estimate differential group delay and/or other channel characteristics based on the equalizer coefficients using a frequency averaging or polarization averaging approach. Framer information can furthermore be utilized to estimate differential group delay that is an integer multiple of the symbol rate. Additionally, a DSP reset may be performed when substantial signal degradation is detected based on the channel diagnostics information.

Abstract: The present invention is directed to data communication systems and methods thereof. According to various embodiments, the present invention provides a communication with a reconfigurable forward-error-correction (FEC) module. The FEC module processes data received from two or more communication lanes, and depending on the mode of operation, the FEC module can combine data from the two or more communication lanes and perform error correction on the combined data, or the FEC module can processes data from the two communications lanes separately and perform error correction independently for the each of the data communication lanes. There are other embodiments as well.

Abstract: The present invention includes an integrated system-on-chip device configured on a substrate member. The device has a data input/output interface provided on the substrate member and configured for a predefined data rate and protocol. The device has an input/output block provided on the substrate member and coupled to the data input/output interface. The input/output block comprises a SerDes block, a CDR block, a compensation block, and an equalizer block. The SerDes block is configured to convert a first data stream of N having a first predefined data rate at a first clock rate into a second data stream of M having a second predefined data rate at a second clock rate. The device has a driver module provided on the substrate member and coupled to a signal processing block, and a driver interface provided on the substrate member and coupled to the driver module and a silicon photonics device.

Abstract: Apparatus and method for digital signal constellation transformation are provided herein. In certain configurations, an integrated circuit includes an analog front-end that converts an analog signal vector representing an optical signal into a digital signal vector, and a digital signal processing circuit that processes the digital signal vector to recover data from the optical signal. The digital signal processing circuit generates signal data representing a signal constellation of the digital signal vector. The digital signal processing circuit includes an adaptive gain equalizer that compensates the signal data for distortion of the signal constellation arising from biasing errors of optical modulators used to transmit the optical signal.

Abstract: An optical dispersion compensator integrated with a silicon photonics system including a first phase-shifter coupled to a second phase-shifter in parallel on the silicon substrate characterized in an athermal condition. The dispersion compensator further includes a third phase-shifter on the silicon substrate to the first phase-shifter and the second phase-shifter through two 2×2 splitters to form an optical loop. A second entry port of a first 2×2 splitter is for coupling with an input fiber and a second exit port of a second 2×2 splitter is for coupling with an output fiber. The optical loop is characterized by a total phase delay tunable via each of the first phase-shifter, the second phase-shifter, and the third phase-shifter such that a normal dispersion (>0) at a certain wavelength in the input fiber is substantially compensated and independent of temperature.

Abstract: The present invention is directed to communication systems and methods. In a specific embodiment, the present invention provides an optical receiver that receives a data stream from an optical transmitter. The optical receiver determines a histogram contour parameter using the data stream and inserts the histogram contour parameter into a back-channel data segment, which is then transmitted to the optical transmitter. The optical transmitter changes its data transmission setting based on the histogram contour parameter. There are other embodiments as well.

Abstract: Embodiments relate to the emulation of the effect of Forward Error Correction (FEC) codes, e.g., GF10 Reed Solomon (RS) FEC codes, on the bit error ratio (BER) of received Pseudo-Random Binary Sequences (PRBS) patterns. In particular, embodiments group errors into RS-FEC symbols and codewords in order to determine if the errors are correctable. By emulating the error correction capabilities of FEC codes in order to determine which errors are correctable by the code, embodiments afford a more accurate representation of the post-FEC BER of RS FEC codes from links carrying PRBS patterns. This FEC code emulation provides error correction statistics, for stand-alone use or for error correction in connection with Bit Error Rate Testers (BERTs).

Abstract: A tunable voltage oscillator expands a voltage oscillator's tuning range and compensate for any frequency spread present in the voltage oscillator. The tunable voltage oscillator multiplies a frequency of a periodic signal generated by the voltage oscillator by a fractional number. This fractional number is determined by a desired frequency range and an actual frequency range of the voltage oscillator. As such, the frequency range of the output periodic signal is tuned into the desired range. The voltage oscillator can include a programmable inductor of which the inductance can be adjusted thereby to expand the frequency range by increasing the quality factor in the low frequency range.

Abstract: A tunable laser device based on silicon photonics includes a substrate configured with a patterned region comprising one or more vertical stoppers, an edge stopper facing a first direction, a first alignment feature structure formed in the patterned region along the first direction, and a bond pad disposed between the vertical stoppers. Additionally, the tunable laser includes an integrated coupler built in the substrate located at the edge stopper and a laser diode chip including a gain region covered by a P-type electrode and a second alignment feature structure formed beyond the P-type electrode. The laser diode chip is flipped to rest against the one or more vertical stoppers with the P-type electrode attached to the bond pad and the gain region coupled to the integrated coupler. Moreover, the tunable laser includes a tuning filter fabricated in the substrate and coupled via a wire waveguide to the integrated coupler.