Abstract: There is disclosed a memory system and method. The memory system may include a plurality of memory planes including two or more data memory areas, and a memory controller adapted to controlling reading, writing, and erasing of the plurality of memory planes. When any one of the data memory areas is occupied with one of a write operation and an erase operation, the controller may reconstruct data stored in the one occupied data memory area by reading parity information and data stored in the plurality of memory areas other than the one occupied data memory area.

Abstract: A load reduction system and method for use with memory systems which include one or more DIMMs, each of which includes a circuit arranged to buffer data bytes being written to or read from the DIMM, with the system nominally organized such that the bytes of a given data word are conveyed to the DIMMs via respective byte lanes and stored in a given rank on a given DIMM. The system is arranged such that the DRAMs that constitute a given rank are re-mapped across the available DIMMs plugged into the slots, such that a data word to be stored in a given rank is striped across the available DIMMs, thereby reducing the loading on a given byte lane that might otherwise be present. The system is preferably arranged such that any given byte lane is wired to no more than two of the DIMM slots.

Abstract: A memory module may include a circuit board connectable to a system memory bus through a plurality of contacts disposed along one edge of the circuit board, the system memory bus having three positions for connecting memory modules. A plurality of memory chips may be mounted on the circuit board. The circuit board may include a plurality of D/Q traces to couple a corresponding plurality of D/Q signals from respective contacts to the plurality of memory chips or to one or more buffer chips that isolate the system memory bus from the memory chips. Each of the plurality of D/Q traces may have a predetermined trace impedance selected to provide a predetermined D/Q signal quality level when the memory module is installed in any of the three positions on the system memory bus and equivalent memory modules are installed in the other two positions.

Abstract: A compensation circuit and method for reducing ISI products within an electrical data signal corresponding to a detected data signal received via a signal transmission medium introduces distinct compensation effects for individual ISI products within the electrical data signal. Distinct data signal components within the detected data signal and corresponding to such ISI products can be selectively and individually compensated, thereby producing a compensated data signal in which each selected one of such individual data signal components is substantially removed. Individual data signal components or selected combinations of data signal components can be compensated as desired.

Abstract: Systems and methods are disclosed to provide channel monitoring and/or performance monitoring for a communication channel. For example, in accordance with an embodiment of the present invention, an equalizer is disclosed that equalizes for channel distortions and also provides channel and performance monitoring information, such as for example bandwidth estimation, channel identification, signal-to-noise ratio, chromatic dispersion, and/or polarization-mode dispersion.

Abstract: Method and system for a high-speed multiplexer with reduced inter-symbol interference are disclosed. In one embodiment of the present invention, two input bit streams are interleaved by a multiplexer to derive an output bit stream. Each input bit stream is latched by a return-to-differential-zero latch that drives its input bit stream to a neutral state when it is not selected by the multiplexer as output. In an alternate embodiment of the present invention, a pre-selector receives two input signals, determines which of the two input signals will be selected as output of the multiplexer and passes the bit stream unaltered, while passing a differential zero value in place of the unselected input bit stream.

Abstract: An output buffer with a switchable output impedance designed for driving a terminated signal line. The buffer includes a drive circuit, and a means for switching the output impedance of the drive circuit between a first, relatively low output impedance when the output buffer is operated in a ‘normal’ mode, and a second output impedance which is greater than the first output impedance when operated in a ‘standby’ mode. By increasing the drive circuit's output impedance while in ‘standby’ mode, power dissipation due to the termination resistor is reduced. When used in a memory system, additional power savings may be realized by arranging the buffer such that the increased impedance in ‘standby’ mode shifts the signal line voltage so as to avoid the voltage range over which a line receiver's power consumption is greatest.

Abstract: An adaptive signal equalizer with a feedforward filter in which the feedback error signal and corresponding incoming data signal are dynamically aligned in time using signal interpolation, and further, to control the precursor/postcursor filter taps configuration, thereby producing more adaptive filter tap coefficient signals for significantly improved and robust signal equalization.

Abstract: A continuous time electronic dispersion compensation architecture using feed forward equalization and a non-linear decision feedback equalization forms an output signal by a linear combination of successively delayed versions of the input signal and the sliced output signal weighted by appropriate coefficients. A selected number of taps in the mixer used to generate a corresponding number of coefficients for use in the feed forward equalizer are held to a selected voltage to ensure that the coefficients associated with these two taps do not drift. This causes the other coefficients to converge to a unique minimum square error value. In one embodiment the selected voltage is the maximum system voltage.

Abstract: A master-slave flip-flop comprises master and slave latches, with the data output of the master latch connected to the data input of the slave latch. The latches receive clock signals CKM and CKS at their respective clock inputs; each latch is transparent when its clock signal is in a first state and latches a signal applied to its input when its clock signal is in a second state. A clock buffer receives an input clock CKin and generates nominally complementary clock signals CKM and CKS such that one latch is latched while the other is transparent. The clock buffer is arranged to skew CKS with respect to CKM such that the slave latch is made transparent earlier than it would without the skew, making the minimum delay (tpd) between the toggling of CKin and a resulting change at the slave latch's output less than it would otherwise be.

Abstract: A programmable strength output buffer intended for use within the address register of a memory module such as a registered DIMM (RDIMM). The output signals of an array of such buffers drive respective output lines that are connected to the address or control pins of several RAM chips. The programmable buffers vary the strength of at least some of the output signals in response to a configuration control signal, such that the output signals can be optimized for the loads to which they will be connected.

Abstract: A PLL circuit provides a self-selecting divide ratio, which is varied as necessary to lock the circuit to a reference clock which may have several possible frequencies, thereby enabling the VCO to employ a type of oscillator having a superior jitter characteristic. The PLL circuit includes a variable divider which divides the VCO output by a divide ratio value provided by a frequency band select circuit, which provides the divide ratio needed to drive the phase difference between the reference and divided clocks toward zero while the VCO clock output operates within a predetermined frequency range. The self-selecting variable divide ratio allows the VCO's oscillator to have a narrow output frequency range, thereby allowing the use of an oscillator type with a jitter characteristic which may be low enough to meet the requirements of JEDEC, for example.

Abstract: A bipolar high impedance element comprises a p-n diode made from a compound semiconductor, and circuitry arranged to reverse-bias the diode such that the diode conducts a nearly constant current—thereby enabling the element to be employed as a high impedance element. The diode is preferably the base-emitter junction of a transistor made from a compound semiconductor like InP, such that an on-chip high impedance element is provided for a fabrication process such as that used for HBTs. The element is suitably employed in an active low pass filter design: the element is connected between an input signal and an op amp input, and a feedback capacitor is connected between the op amp's output and input. The resulting filter's time constant varies with the reverse-biased diode's impedance and the capacitance of the feedback capacitor.

Abstract: Method and system for reducing parasitic feedback and resonances in high-gain transimpedance amplifiers. In a first embodiment of the present invention, a resistive layer is implemented in the gaps of a high-gain transimpedance amplifier's metallic planes. In a second embodiment of the present invention, a resistive layer is implemented underneath a high-gain transimpedance amplifier's ground plane, vias are implemented to create contact between the resistive layer and the ground plane.

Abstract: A fast, high-swing driver circuit for driving an electro-optical modulator includes an output stage comprising first and second transistors arranged as a differential pair. The collector of the first transistor is coupled to ground, and its base provides the stage's input. The collector of the second transistor is coupled via an impedance to a supply voltage, and provides the stage's output. A reference voltage is provided to the second transistor's base, which is also AC-coupled to ground. A bias generator provides the second transistor's base voltage, and a second differential pair converts a differential input signal to a single-ended output that drives the output stage's input—preferably via a pair of cascaded emitter-follower stages that serve to present a low impedance. A complete electro-optical modulator driver is formed with the addition of a bias-T network at the output stage's output.

Abstract: An output buffer for driving a capacitively-terminated transmission line produces a waveform which comprises a first portion during which the waveform transitions from a voltage V1 to a voltage V2; a second portion during which it remains fixed at V2; a third portion during which it transitions to a voltage V3; and a fourth portion during which it remains fixed at V3. The waveform is created within a unit interval whenever successive data bits transition between logic states. The first and second portions are generated with circuitry arranged such that V2 is maximized by reducing the buffer's output impedance. The fourth portion is generated with circuitry which has a non-zero output impedance preferably equal to the transmission line's characteristic impedance, to absorb transitions reflected back to the source circuitry by the capacitive termination.

Abstract: A method and apparatus for improving the performance of an edge launch electrical connector. Two or more edge vias are established along an edge face of a planar circuit module, such as a single- or multi-layer PCB, integrated circuit on a ceramic or organic substrate or a ceramic or organic package, thereby providing a short path from one or more of the substrate assembly's ground planes to a ground associated with the edge launch electrical connector, reducing jitter and providing a solution with low insertion and return losses. The two edge vias may be standard vias, castellations or wires or lines deposited, printed, painted, secured or put in contact with an edge face of the planar circuit module and are arranged at each side of the signal line thereby providing additional electromagnetic shielding. Optionally, an air line may be established to increase the operational cut-off frequency and/or improve electrical performance.

Abstract: A robust output buffer component capable of providing high quality output signals comprising a cascode module for receiving a differential signal from a differential pair module and transmitting that differential signal as two output waveforms. Using a bipolar implementation example, the emitter end of a common base cascode pair is coupled to the collector end of a common emitter differential pair with an optional resistive module inserted between the cascode pair and the differential pair. Engineering the cascode bias, the resistance at the collector nodes of the differential pair and/or the resistance at the base nodes of the differential pair effects: the degree of non-linearity of the base-collector capacitance as a function of the base-collector voltage, the voltage swing of the collector nodes, and the degree of symmetry of the input voltages. These three parameters may be used to optimize the symmetry of the output waveforms.

Abstract: Method and system for a diode shunting configuration wherein the configuration prevents a transimpedance amplifier from saturation while maintaining high transimpedance gain and bandwidth. In one embodiment of the present invention, a diode is coupled to the input of a transimpedance amplifier in order to prevent the transimpedance amplifier from saturation. Moreover, the diode serves to divert current such that in cases where the input current is low the diode never turns on and only represents a minimal, mostly capacitive load on the input; in cases where the input current is high, the diode conducts and diverts any excess input current from the transimpedance amplifier.

Abstract: An electronic apparatus with a high inductive reactance for differential signals per unit area and a small inductive reactance for common-mode signals relative to its inductive reactance for differential signals with predictable and scalable characteristics. This may be achieved by configuring transmission line pairs such that currents associated with the differential component of a source signal in the first and second transmission lines are aligned and currents associated with the common mode component of a source signal in the first and second transmission lines are counter-aligned. Advantageously, the current invention may be implemented using currently available technology and integrated into a variety of different devices such as broad-band and narrow-band amplifiers, high-speed logic gates, mixers, oscillators, wireless local area networks, global positioning systems and modern communication systems.