Abstract: A Platform Environment Control Interface (PECI) signal interconnection method and system for a server, a computer device and a readable storage medium are provided. The method includes: acquiring a partition mode of the server; sending a corresponding first control signal and a corresponding second control signal to each computing node according to the partition mode; controlling a channel selection of a first switch on the corresponding computing node by the corresponding first control signal and controlling a channel selection of a second switch on the corresponding computing node by the corresponding second control signal; and transmitting PECI signals of the corresponding computing node through channels connected by the first switch and channels connected by the second switch. According to the described solution, interconnection routing of the PECI signals in a single-partition mode and a dual-partition mode may be achieved by using only one backplate.

Abstract: A server Joint Test Action Group (JTAG) component adaptive interconnection system and method. The system includes a JTAG master device, a programmable device, and a plurality of JTAG components. The programmable device is configured to simulate JTAG timing according to a JTAG protocol and test JTAG channels of the JTAG components connected to the programmable device one by one. The programmable device connects in series a Test Data Output (TDO) signal of a previous JTAG component with a Test Data Input (TDI) signal of a next JTAG component in the programmable device, connects a TDI signal of a first JTAG component with a TDI signal of the JTAG master device, and connects a TDO signal of a last JTAG component with a TDO signal of the JTAG master device, so as to form a JTAG interconnection chain.

Abstract: A method and device for testing a conversion relationship between different reading manners in a flash memory chip and a readable storage medium are provided. Block reading is respectively performed, a bit error rate file is recorded, a test starting point, a test ending point and a test step length are is set in a block, the bit error rate file of the number of times of corresponding page reading is respectively recorded, and the number of times of page reading that is closest to the proportion of block error codes are found from the proportion of page error codes, a conversion of the number of times of block reading and the number of times of page reading is completed, conversion coefficients of the block reading and the page reading can be calculated for blocks in different states of a life cycle.

Abstract: A direct-current power supply parallel-machine input reverse connection prevention circuit and a server. The circuit comprises a first switch tube, second switch tube (Q2). A first end of the first switch tube is used for being connected to a positive end of a first power supply and a second end of the first switch tube is connected to a positive input end of a first driving module. A first end of the second switch tube is used for being connected to a positive end of a second power supply and a second end of the second switch tube is connected to a positive input end of a second driving module.

Abstract: A key management method and a related device are provided. The method includes: receiving key generation request information; generating attribute access policy information on the basis of the key generation request information, the attribute access policy information being an attribute set for encrypting a data key; encrypting the data key on the basis of the attribute set for encrypting the data key; receiving key acquisition request information; on the basis of the attribute set for encrypting the data key, verifying whether attribute information of the key acquisition request information is included in the attribute set for encrypting the data key; and in response to the attribute information of the key acquisition request information being included in the attribute set for encrypting the data key, acquiring a destination data key on the basis of the attribute information of the key acquisition request information.

Abstract: A signal correction circuit and a server are provided. The circuit comprises: a first signal processing component receiving an input signal and positive power supply voltages and negative power supply voltages, generating a first control voltage, and outputting a first voltage, the first voltage being zero within a first time period; a second signal processing component generating a second control voltage according to the first control voltage, performing energy storage charging according to the second control voltage, controlling an energy storage charging voltage according to the second control voltage, and outputting a second voltage, and the second voltage being zero in the second time period; and an output component performing superposition processing on the first voltage and the second voltage to obtain an output signal.

Abstract: A PCIe switch working mode updating method and apparatus, an electronic device, and a computer-readable storage medium, which are applied to a controller. The PCIe switch working mode updating method includes: determining a required switch firmware version of a system according to system configuration information; determining the current switch firmware version according to the current port definition state of a PCIe switch; determining, according to the required switch firmware version and the current switch firmware version, whether a switch port reallocation operation needs to be executed; and under the condition that the switch port reallocation operation needs to be executed, sending, to the PCIe switch, a data file corresponding to the required switch firmware version, so that the PCIe switch updates a working mode according to the data file.

Abstract: The disclosure provides a server cabinet, including: a cabinet frame, first mounting flanges detachably and vertically arranged at two sides of a front end of the cabinet frame, second mounting flanges detachably and vertically arranged at the two sides of the front end of the cabinet frame, first support brackets detachably arranged at the two side walls of the cabinet frame and configured for installing an ODCC server, and second support brackets detachably arranged at the two side walls of the cabinet frame and configured for installing an OCP server; wherein a plurality of first mounting holes configured for being matched with a front end of the ODCC server are formed in the first mounting flanges along a height direction, and a plurality of second mounting holes configured for being matched with a front end of the OCP server are formed in the second mounting flanges along the height direction.

Abstract: A task scheduling method includes: when a task requirement is obtained, splitting the task requirement to obtain the plurality of subtasks having a constraint relationship; performing execution condition detection on non-candidate subtasks, determining a non-candidate subtask that satisfies an execution condition as a candidate subtask, and putting the candidate subtask into a task queue; performing state detection on a server network composed of edge servers to obtain server state information and communication information; inputting the server state information, the communication information, and queue information corresponding to the task queue into an action value evaluation model to obtain the plurality of evaluated values respectively corresponding to the plurality of scheduling actions; and determining a target scheduling action from the plurality of scheduling actions by using the evaluated values, and scheduling the candidate subtask in the task queue on the basis of the target scheduling action.

Abstract: An image compression sampling method and assembly are provided. The method includes: performing sparse representation on a target image by using an initial sparse matrix, quantifying an initial sparse representation result to obtain an optimized sparse representation result, and obtaining an optimized sparse matrix; constructing a product matrix by using the optimized sparse matrix and an initial measurement matrix, and adjusting absolute values of off-diagonal elements in the product matrix to be less than a correlation threshold; performing singular value decomposition on the product matrix to obtain a diagonal matrix and a left singular matrix, and updating the diagonal matrix according to a quantity of samplings of the initial measurement matrix; and optimizing the initial measurement matrix by using the left singular matrix and the updated diagonal matrix to obtain an optimized measurement matrix, and collecting image data by using the optimized sparse matrix and the optimized measurement matrix.

Abstract: This application discloses a high-reliability protection circuit and a power supply system.

Abstract: Provided is a data processing method, which includes: in response to a logical volume receiving a write request, whether a logical address carried in the write request is occupied by a data unit in the logical volume is determined; if not, a data grain which is closest to the size of a data block and is greater than the size of the data block is determined; a new data unit is created in the logical volume by use of the logical address as an initial address and by use of the closest data grain as the length, and a logical address range occupied by the data block in the new data unit is recorded; the data block is written into an underlying storage and a written physical address is returned; and a mapping relationship between the initial address and the physical address is established and saved.

Abstract: Provided are a chip and a pin line-out design method therefor, which are applied to a BGA packaged chip. The method includes: according to pin position information and pin definition information of a chip, determining a number of circuit board layers required for pin line-out of the chip (S1); allocating line-out layers to pins of the chip in their respective circuit boards (S2); and according to a pin density and transmission line width requirement of the chip, determining a specification of a via hole in each circuit board for leading the pin of the chip out to the corresponding line-out layer, to perform a corresponding line-out design on the basis of the via hole (S3). It may be seen that the described unified pin line-out design for the BGA packaged chip is more refined, and the quality of the line-out design of the pins of the chip is ensured.

Abstract: A method and device for model compression of a neural network. The method comprises: recording input and output parameters of each layer of network in a network structure; dividing the network structure into several small networks according to the input and output parameters; setting a pruning flag bit of a first convolutional layer in each small network to be zero to obtain a pruned small network; training each pruned small network to obtain a network weight and a weight mask; recording a pruned channel index number of each convolutional layer of a pruned small network with the weight mask of zero; and carrying out decomposition calculation on each pruned small network according to the pruned channel index number. According to the method, a calculation amount and the size of a model is reduced, and during network deployment, the model can be loaded with one click, thus reducing usage difficulty.

Abstract: The present disclosure discloses a method for determining a PCIe signal bandwidth, apparatus and device, and a computer readable storage medium. A target frequency point at which the energy spectrum density of a PCIe signal of a transmission link to be measured, after an output signal of said transmission link is subjected to inverse Fourier transform, reaches a preset proportion (determined according to a measurement error requirement of said transmission link) of that of an original signal is obtained by testing, and the target frequency point is taken as a bandwidth of the PCIe signal of said transmission link. Therefore, accurate high-speed signal bandwidth selection is realized.

Abstract: Provided is an image processing method, which includes: determining whether the number of written rows of source image data in a DDR is a preset number of rows or a stop write number of rows, the preset number of rows being an integer multiple of the number of rows of an image block determined according to a compression condition, and the image block being any image block in an image block matrix determined on the basis of an entire frame of image; if yes, reading the source image data of the current image block from the DDR on the basis of a first read address of the current image block, the number of rows, and the number of columns; and performing compression on the source image data of the current image block to obtain compressed data, and writing the compressed data to the DDR.

Abstract: A virtual machine management method and apparatus, a device, and a readable storage medium. The virtual machine management method is applied to a private cloud, and comprises: acquiring a SELinux label, the SELinux label comprising five elements: User, Role, Type, Sensitivity, and Category (S101); setting elements other than Category in the SELinux label as default values (S102); assigning different values to Category according to a preset Category variable combination so as to obtain multiple non-duplicate label groups (S103); and configuring each label group to a virtual machine in the private cloud, so that virtual machines configured with the same label group communicate with each other, and virtual machines configured with different label groups are isolated from each other (S104).

Abstract: Provided is a FPGA-based design method for equally dividing an interval, including the following steps: dividing the oscillation periods of a second pulse signal of a crystal oscillator clock of a FPGA board by the number of equally divided sampling pulses, and obtaining the remainder thereof; dividing the remainder by the number of the equally divided sampling pulses to serve as an error within each sampling interval; using a counter to count from the second pulse, and stopping the counting of the counter once whenever the error within the sampling interval, which is accumulated within the second pulse interval, is greater than or equal to the vibration period. Further provided is a FPGA-based design device for equally dividing an interval. The present application makes full use of the feature of interval equal division calculation, has high precision, and is easy to implement.

Abstract: Provided is a dynamic Huffman encoding method based on a sorting network. Compared with traditional dynamic Huffman coding solutions, the method implements sorting on the basis of the sorting network, therefore the sorting process is not only stable, but also may ensure a stable sorting result; and moreover, sorting steps and related operations are simpler, thereby greatly simplifying the sorting and iteration processes, and thus the sorting efficiency is higher. In addition, the sorting process better facilitates program implementation and transplantation, and implementation of hardware and software may achieve good effects. In addition, the present disclosure further provides a dynamic Huffman coding apparatus and device based on a sorting network, and a readable storage medium, and the technical effects thereof correspond to the technical effects of the above method.

Abstract: A power supply device with dual power source planes and a server. The device includes: a plurality of controllers connected in parallel; a first Power Supply Unit (PSU) power source group and a second PSU power source group each includes two PSU power sources connected in parallel, and the first PSU power source group and the second PSU power source group are respectively located on two independent power source planes; and a power source backboard, wherein the power source backboard includes a first copper skin layer and a second copper skin layer, which are not connected with each other, the first PSU power source group is connected to the input end of each controller by means of the first copper skin layer, and the second PSU power source group is connected to the input end of each controller by means of the second copper skin layer.