Abstract: A password hardcoding checking method and apparatus based on PCA, and a medium. the checking method includes: step one, data collection, involving: collecting function code blocks in which data of password hardcoding that is subject to a false alarm is located; step two, extracting feature values in the function code blocks collected in step one, so as to obtain a feature set; step three, using the function code blocks collected in step one to serve as samples to construct a PCA model; and step four, on the basis of the PCA model constructed in step three and the feature set obtained in step two, detecting whether there is a false alarm in password hardcoding. by means of the method, the false alarm rate of hardcoding checking in code scanning is reduced, and the working efficiency of a developer and a code auditor is improved.

Abstract: A method, apparatus, and device for erasing a Solid State Disk (SSD), and a storage medium are provided. The method includes: receiving, from a Virtual Flash Translation Layer (VFTL) running in a preset virtual environment, an erasing request for erasing a target block; selecting a target spare block from preset spare blocks and feeding back the target spare block to the VFTL; collecting running information of the VFTL within a preset period of time, and determining whether a function of the VFTL is normal according to the running information; and in a case of determining that the function of the VFTL is normal, performing an erasing operation on the target block. The method may fully and comprehensively detect the abnormal condition of the VFTL, and may guarantee the integrity of data information in the solid state disk, thereby improving the reliability of the solid state disk.

Abstract: Provided are a Reduced Instruction Set Computer-Five (RISC-V)-based artificial intelligence inference method and system. The RISC-V-based artificial intelligence inference method includes the following steps: acquiring an instruction and data of artificial intelligence inference by means of a Direct Memory Access (DMA) interface, and writing the instruction and the data into a memory; acquiring the instruction from the memory and translating the instruction, and loading the data from the memory to a corresponding register on the basis of the instruction; in response to the instruction being a vector instruction, processing, by a convolution control unit, corresponding vector data in a vector processing unit on the basis of the vector instruction; and feeding back the processed vector data to complete inference.

Abstract: The present disclosure discloses a method for Huffman correction and encoding, a system and relevant components, wherein the method includes: obtaining a target data block in a target file; constructing a Huffman tree by using the target data block; determining whether a depth of the Huffman tree exceeds a preset value; and when the depth of the Huffman tree does not exceed the preset value, by using the Huffman tree, generating a first code table and encoding the target data block; or when the depth of the Huffman tree exceeds the preset value, by using a standby code table, encoding the target data block; wherein the standby code table is a code table of an encoded data block in the target file.

Abstract: The present application relates to an adaptive PAM4 decision feedback equalization circuit, including a decision feedback equalization main circuit and an adaptive circuit. The main circuit includes an adder, a first decision device, a second decision device, a third decision device, a first delay unit group, a second delay unit group, a third delay unit group, a decoder, and a DSP coefficient table; the adaptive circuit includes an eye pattern monitoring module and an adaptive module; and the adaptive module includes a comparison unit, a delay unit, and a coefficient regulation and control unit.

Abstract: A method, system and apparatus for monitoring a BIOS booting process of a server. The method includes: detecting whether a PCH in a server starts to transmit data to a BMC; when the PCH starts to transmit data to the BMC, acquiring data from an IO transmission line between the PCH and the BMC and parsing same, and determining whether the parsed data includes process data which represents a BIOS booting process of the server; and when the parsed data includes the process data, displaying the process data. It can be seen that a user may directly and quickly determine the current booting process of a BIOS by means of displayed information, such that quick trouble locating of a server during a BIOS booting process is facilitated.

Abstract: Disclosed is a JTAG-based burning device, including controllable switches arranged between a TDI terminal of a JTAG host and a first chip, and between two adjacent chips, and further including a master controllable switch module arranged between each chip and a TDO terminal of the JTAG host, wherein the JTAG host may, according to a received burning instruction, control corresponding input terminals of the controllable switches to be connected to corresponding output terminals and also control an output terminal of the master controllable switch module to be connected to the corresponding input terminal. Obviously, a JTAG chain can be automatically adjusted by controlling the connection relationship between input and output terminals of the corresponding switches by only building a circuit, so that firmware burning on different chips or chip combinations is realized without manual adjustment, thereby improving the test efficiency, and simplifying the circuit structure.

Abstract: A far-end data migration device and method based on a FPGA cloud platform. The device includes a server, a switch, and a plurality of FPGA acceleration cards. The server transmits data to be accelerated to the FPGA acceleration cards by means of the switch. The FPGA acceleration cards are configured to perform a primary and/or secondary acceleration on the data, and are configured to migrate the accelerated data. The method includes: transmitting data to be accelerated to a FPGA acceleration card from a server by means of a switch; performing, by the FPGA acceleration card, a primary and/or secondary acceleration on the data to be accelerated; and migrating, by the FPGA acceleration card, the accelerated data.

Abstract: An automatic driving simulation task scheduling method and apparatus, a computer device, and a readable storage medium. The method includes: constructing a network flow block diagram on the basis of the number of cluster racks, the number of nodes, and the number of processes, and coding information of the network flow block diagram (S01); setting information of a task to be simulated, and performing shortest path computation on a simulation task flow by means of the network flow block diagram (S02); and updating the state of a scheduling system in real time according to a fair policy and a preemptive scheduling policy, and executing scheduling on the basis of the state of the scheduling system (S03).

Abstract: Disclosed in the present disclosure is a command information transmission method, applied to a Physical Function (PF) port. The method includes: parsing a received interrupt request to obtain a target Virtual Function (VF) port; determining a target physical-side interrupt handler corresponding to the target VF port; obtaining target command information corresponding to the target physical-side interrupt handler in a device memory overlap region, where the device memory overlap region is an overlap region obtained by performing memory mapping on the PF port and each VF port in a host address space by a device memory overlap mapping technology; and executing switching to the target physical-side interrupt handler, and performing a response operation on the target command information.

Abstract: Provided are a read-write method and apparatus, an electronic device, and a readable memory medium. The method includes: receiving a write instruction; determining a write policy corresponding to the write instruction according to read information in a registry, wherein the read information is information that, after a read instruction is received, corresponds to the read instruction and is stored in the registry; and executing the write instruction based on the write policy. It can be seen that, according to the present application, a registry is set, read information is registered in the registry when a read instruction is executed, a write policy corresponding to a write instruction is determined according to the read information in the registry before the write instruction is executed, and the write instruction is then executed based on the write policy. Therefore, the read-write processing efficiency is improved.

Abstract: A register reading method and apparatus, a device and a medium. After a server is crashed, a CPU-register collecting request is triggered. Different types of CPUs correspond to different types and quantities of registers that require data collection. Therefore, by firstly determining the register required to be read corresponding to the CPU type, and determining the reading mode of the register, the disadvantage that the reading mode that may merely use a single instruction may not satisfy the demand on field crashing analysis is prevented. Subsequently, by using a PECI bus, the register data of a plurality of registers are read. By collecting the registers of the CPU directly by using the PECI bus, the problem that the performance excessively relies on the stability of the ME due to the intermediate transfer via the ME is prevented, which greatly increases the reading success rate of the registers.

Abstract: A method and apparatus for performing a power stress test on an FPGA acceleration card and a computer-readable storage medium. The method includes: dividing, according to a partial reconfiguration method, a hardware resource of an FPGA acceleration card into a static region serving as a hardware logic implementation region for performing a normal function test, and a dynamic PR region including a blank mode occupying no hardware resource and a power test mode for performing a power stress test, and burning FPGA firmware having a partial reconfiguration function to a flash memory; upon receiving a request for power stress test, configuring an operation mode of the dynamic PR region to be the power test mode, loading, to the dynamic PR region, a dynamic PR configuration file burned in the flash memory; and calling a power stress test module to execute the power stress test in the dynamic PR region.

Abstract: A service orchestration method, apparatus and device for a physical machine, and a computer-readable storage medium. The method includes: creating a physical machine resource that inherits all attributes of a cloud host, and modifying the physical machine resource according to characteristics of a target physical machine to obtain a target physical machine resource; configuring an underlying driver of Ironic according to the characteristics of a target physical machine; and invoking the Ironic by means of nova, such that the target physical machine resource is used to perform service orchestration on the target physical machine when the Ironic is running. On the basis of implementing service orchestration on a physical machine, the target physical machine resource in the method is obtained by inheriting all attributes of a cloud host and performing modification according to the characteristics of a target physical machine.

Abstract: Provided is a control circuit of a buck converter, comprising three transistors, seven resistors and a comparator. Also provided is a server. In this solution, when a phase voltage of a buck converter changes, a controller in the buck converter is controlled to output a signal for turning off a lower MOS transistor, so that after the signal is transmitted through the line, the lower MOS transistor can be controlled to be exactly turned off just when the current is reversed. Such an accurate reverse current detection function can reduce the voltage loss of the buck converter, thereby improving the efficiency of a system in standby or having a light load.

Abstract: A method, system, and related component for detecting properness of a PG pin power-on timing sequence are provided. The method comprises: obtaining a pull-up level of a PG pin of a VR chip (S101); determining a value of a pull-up resistor of the PG pin, as a first resistance, when a current injected into the VR chip by using the pull-up level is equal to a maximum withstand current of the VR chip (S102); obtaining an equivalent resistance to ground when the PG pin is at a low level, and calculating, based on the equivalent resistance to ground, a value of the pull-up resistor of the PG pin, as a second resistance, when an output voltage of the PG pin is equal to a preset interference voltage limit value (S103); and outputting first prompt information when it is determined that an actual resistance of the pull-up resistor is lower than the first resistance or the second resistance (S104).

Abstract: A heat dissipation control method is disclosed, wherein the heat generation speed of a heat dissipation channel may be calculated according to a power consumption value of each component in the heat dissipation channel, and a radiator is then controlled on the basis of the heat generation speed, whereby the heat dissipation speed of the heat dissipation channel is comparable to the heat generation speed. A heat dissipation control apparatus and device are further disclosed, which have the same beneficial effects as the heat dissipation control method.

Abstract: A method and device for detecting a memory downgrade error. The method comprises: capturing and analyzing a memory error by means of an operating system (OS); sending a memory downgrade error log to a management chip BMC on a server motherboard according to the analysis result; and after the BMC receives log information, detecting and locating an uncorrectable memory inspection error on the basis of an algorithm.

Abstract: A method and device for avoiding abnormal signal oscillation in UVLO test, applied to a power supply module, includes: a voltage detection module (301) detecting a voltage of an enable terminal of the power supply module during an under voltage lock out UVLO test; a difference calculation module (302) calculating a difference value between a detected voltage and a voltage trigger threshold of the enable terminal; upon a control module (303) determining that the difference value is below a preset first threshold, the control module increasing the voltage of the enable terminal during UVLO test via a voltage adjustment module. The application of the above solution of the present application can avoid abnormal signal oscillation in UVLO test.

Abstract: A method for clearing a register, including: causing the PLD to set preset bits of a first register and a second register as an invalid state, detect whether a command is received from a MCU; when the command being received, parsing the command and determining whether a reading or writing event is triggered; when the reading event being triggered, setting the preset bit of the first register as a valid state, reading data of the preset bit of the first register, postponing clearing, by the PLD, the preset bit of the first register for a preset time; when the writing event being triggered, setting the preset bit of the second register as the valid state, writing, by the MCU, data into the preset bit of the second register, causing the PLD to acquire the data, postpone clearing the preset bit of the second register for a second preset time.