Abstract: A solid state disk access method includes: determining, in response to a read error, a first read voltage of the current data block according to a current data storage time interval to which a data storage time of the current data block belongs; performing reread error correction on the data in the current data block based on the first read voltage; determining, if reread error correction of the current data block fails, a second read voltage corresponding to the current data block according to the current data storage time interval and a preset data read rule that is determined based on the data storage time interval and the number of data reads; and performing reread error correction on the data in the current data block based on the second read voltage until the reread error correction of the current data block meets a preset reread error correction condition.

Abstract: Provided are a method and system for achieving high availability of service under a high-load scene in a distributed system. The method includes constructing a node selection model at a master node of a distributed cluster; constructing a request selection model in each slave node; wherein the request selection model includes weights of designated requests and trade-off parameters set for requests each having a weight greater than a set value; when the distributed system enters the high-load scene, reading, by the master node, the node selection model, and sequentially selecting the served slave nodes according to a time slice round robin policy; and reading, by each slave node, the request selection model, and sequentially returning data of each request according to the trade-off parameters of each request.

Abstract: A system for controlling a fan is provided, which includes a processor, a driver, a power supply module, an instruction output module and a level control module. The power supply module is configured to supply power to the level control module when the server is started up and when the server is shut down. The instruction output module is configured to output a mode control instruction. The level control module is configured to output a first level to the PWM pin and output a second level to the TACH pin based on the mode control instruction and then control the power supply module to supply power to the processor and the driver. The processor is configured to determine a mode of the fan based on the first level and the second level and control a rotation speed of the fan based on the mode of the fan.

Abstract: A network adapter node performance detection method, includes: creating corresponding path test messages based on a plurality of ports of a node to be tested respectively, and sending the corresponding path test messages to a test node by means of the plurality of ports; receiving a path test message returned by the test node, and determining whether a port corresponding to the received path test message is consistent with a receiving port; in response to the fact that the port corresponding to the received path test message is consistent with the receiving port, sending a plurality of performance detection messages to the test node by means of the port; and receiving a performance detection message returned by the test node, and recording a performance parameter of the node to be tested to evaluate a state of the node to be tested.

Abstract: An SPD-based memory monitoring and service life prediction method and system. Said method includes: acquiring parameter information of each memory bank in a server, and setting a weight for the parameter information; reading configuration information of each memory bank, and calculating occupation ratio information of parameters of each memory bank according to the configuration information and the parameter information; calculating state information of each memory bank according to the weight and the occupation ratio information; determining an influence factor according to the number of CPUs in the server and the number and position of memory banks in each CPU; and calculating a final memory state value according to the influence factor and the state information, and according to the used time and the state information of each memory bank, calculating the remaining service life of each memory bank by means of piecewise fitting using a least square method.

Abstract: The present disclosure relates to a baseboard management controller (BMC)-based switch monitoring method, a system, a computer device, and a readable medium thereof. The BMC-based switch monitoring method includes: virtualizing a multi-core BMC into a plurality of logical computers such that each core operates separately; in response to start of a switch, migrating functions of the switch into a first core of the multi-core BMC for start, and monitoring other cores of the multi-core BMC based on a second core of the multi-core BMC; determining, in response to that a new service is received by the switch is detected, whether the new service is a firmware upgrade service; and allocating the new service to the second core in the multi-core BMC for operation, in response to that the new service is the firmware upgrade service.

Abstract: A polling method for server sensors, a polling system for server sensors, and a computer-readable memory medium. The polling method includes: when a BMC is activated, acquiring attribute information of sensors (S101); classifying the sensors according to polling cycles in the attribute information (S102); adding the sensors with the same polling cycle into a same preset data structure (S103); and polling the sensors in the preset data structure using a thread (S104). According to the method, the problem of low polling efficiency caused by polling sensors with different cycles using a single thread may be solved, and each sensor may be polled independently while minimizing influences between polling of the sensors.

Abstract: Disclosed are a service processing method and apparatus, an electronic device, and a computer-readable storage medium. The method includes: when receiving a User Interface (UI) request, creating a process instance corresponding to the UI request, and storing instance information of the process instance in a storage module (S101); determining a target process instance from the storage module, and determining a step to be executed of the target process instance based on target instance information of the target process instance (S102); searching, from a register, and executing a target method corresponding to the step to be executed, wherein the register includes all methods compiled according to a preset development specification (S103).

Abstract: Disclosed is a data set and node cache-based scheduling method, which includes: obtaining storage resource information of each host node; in response to receiving a training task, obtaining operation information of the training task, and according to the operation information and the storage resource information, screening host nodes that satisfy a space required by the training task; in response to no host node satisfying the space required by the training task, scoring each host node according to the storage resource information; according to scoring results, selecting, from among all of the host nodes, a host node to be executed that is used to execute the training task; and obtaining and deleting an obsolete data set cache in the host node to be executed, and executing the training task in the host node to be executed.

Abstract: A control method for a power source, including the following steps: detecting the electric power quality of multiple channels of inputs of a power source; in response to the electric power quality of the multiple channels of inputs being normal, acquiring and comparing the resistance of a relay when the power source is respectively working at each channel of input; in response to the resistance of the relay at each channel of input meeting a preset condition, acquiring the duration how long each power source is working at one channel of input among the multiple channels of inputs; and in response to the duration how long the power source is working at the channel of input in the multiple channels of inputs being greater than a threshold value, adjusting the power source to work at other channel of input.

Abstract: An operation behavior monitoring method includes: obtaining target historical operation behavior data of a target user, and performing data statistics on the target historical operation behavior data according to different dimensions, to build a multi-dimensional coordinate system; when a target operation behavior is received, determining a target data item corresponding to the target operation behavior in each dimension, determining whether a labeling point corresponding to the target data item exists in the multi-dimensional coordinate system or not; if yes, increasing the density of the labeling points by one; if not, determining a labeling point corresponding to the target data item in the multi-dimensional coordinate system, and setting the density of the labeling point to be 1; and calculating a center-of-gravity position corresponding to each coordinate axis according to the density of all the labeling points on each coordinate axis, determining a target point based on all the center-of-gravity positio

Abstract: A method includes: performing, at a preset initial speed, data deletion on a queue with the maximum length in the cache space (S1); in response to the length of the queue with the maximum length and subjected to the data deletion being equal to the lengths of multiple queues in the cache space, triggering data deletion on the plurality of queues (S2); calculating an allocation speed (S3); performing, at the allocation speed, data deletion on each queue, the data deletion of which is triggered (S4); in response to the lengths of all queues subjected to the data deletion being equal to the lengths of multiple other queues in the cache space, triggering the data deletion on the plurality of other queues, and returning to calculating the allocation speed (S5); and in response to triggering the stopping of diluting the cache space, pausing a data deletion process (S6).

Abstract: The present disclosure is to propose a method and device for improving a link aggregation protocol timeout. method for improving a link aggregation timeout. The method includes the following steps: setting a timeout value and a timeout threshold count of link aggregation control protocol data unit (LACPDU) packet reception of a switch; obtaining a timeout count statistically, in response to a timeout of reception of a link aggregation control protocol data unit (LACPDU) packet from a second switch by a first switch; determining, through a network controller, in response to that the timeout count is greater than the timeout threshold count and that an aggregated link between the switches is in an out-of-band management mode, whether a port of the second switch is abnormal; and removing, in response to the port of the second switch being abnormal, the abnormal port of the second switch from the aggregated link.

Abstract: A neural network accelerating method and device includes: reading a total video memory size available for a GPU to execute computing of a neural network, setting a size of a configurable level, and determining a finest granularity of a factor used for splitting a workspace; generating an optimal acceleration solution architecture for determining an optimal batchsize and an optimal network layer configuration that enable fastest convolution execution; generating a state transition equation for a multiple knapsack problem by taking a convolution operation efficiency boundary condition in the optimal acceleration solution architecture as a fitness function; iterating the state transition equation by using a genetic algorithm taking a forward and back convolution function as evaluation bases until a convergent batchsize and network layer configuration are obtained, and accelerating the neural network by taking the convergent batchsize and the network layer configuration as the optimal batchsize and the optimal ne

Abstract: A method for supporting TCM communication by a BIOS of an ARM server, including: setting an access mode of a LPC bus device to a 4-byte mode by means of a BIOS of an ARM server; causing the BIOS to perform data communication with a TCM chip of the LPC bus device in the 4-byte mode; in response to the BIOS reading a register by means of the LPC bus device, determining a type of the register; in response to determining that the type of the register is a specific FIFO register, changing a control register from the 4-byte mode to a single-byte mode, and performing single-byte read-write on the specific FIFO register; and in response to completion of read-write of the specific FIFO register, changing the control register to the 4-byte mode by means of the BIOS, and performing a read-write operation on other FIFO registers.

Abstract: Disclosed is an Avalon-to-Axi4 bus conversion method, including: in case that an Avalon bus is an Avalon_st bus, receiving Avalon_st bus data, performing a logical process on the received Avalon_st bus data, and then outputting corresponding Axi4_st bus data; and in case that the Avalon bus is an Avalon_mm bus, receiving a signal transmitted by each channel of the Avalon_mm bus, framing and storing the signal in asynchronous First Input First Output (FIFO), and in case that a device corresponding to an Axi4 bus is ready, reading the signal from the asynchronous FIFO, and outputting the signal to a corresponding channel of the Axi4 bus according to a timing relationship of the Axi4 bus.

Abstract: The control circuit includes a signal indication circuit, a control/isolation circuit, and an energy storage circuit; the signal indication circuit is a logic AND gate circuit, has an input end connected to multiple paths of power-down monitoring signals and an output end connected to an input end of the control/isolation circuit, and when a level of any path of power-down monitoring signal is low, outputs a low level to the control/isolation circuit; an output end of the control/isolation circuit is connected to an enable end of a Direct Current (DC) power chip, and the control/isolation circuit controls and isolates an output signal of the signal indication circuit by means of two-stage Metal-Oxide-Semiconductor (MOS) transistors; and an output end of the energy storage circuit is connected to the control/isolation circuit to provide reserve power for operation of the MOS transistors of the control/isolation circuit.

Abstract: A data center 5th-Generation (5G) network encrypted multicast-based authority authentication method, system, and device, and a medium. In the present disclosure, authority authentication and data connection are performed on each platform of a data center by 5G network encrypted multicast, and a network encrypted multicast component is configured on the platform of the data center. An encrypted multicast packet is sent to a network by the platform. Connection is completed by handshaking and mutual heartbeat transmission between the platforms. Authority verification is performed through the multicast packet. In this manner, the problem of security risk of traditional authority authentication may be reduced, and the intercommunication speed and efficiency of each platform of the data center may be improved greatly.

Abstract: Disclosed is a method and chip for vertically filtering an image, including: caching and reading image data; calling a filter to vertically filter the image data to obtain first filtered data; updating the image data according to the first filtered data, and judging whether a to-be-read row is the last row of the image data; if not, updating the to-be-read row to the next row of the to-be-read row, and returning to execute the step of caching the image data; and if so, determining the vertically filtered image data. In the present application, point-by-point feedback is changed to row-by-row feedback according to an algorithm principle of a digital recursive filter and the characteristics of an image chip.

Abstract: Disclosed are a power consumption reduction circuit for Graphics Processing Units (GPUs) in a server and a server. The power consumption reduction circuit includes a frequency reduction control chip. The frequency reduction control chip, after receiving an overpower alarm signal generated by a Power Supply Unit (PSU), generates a frequency reduction control signal to a Power Break (PWRBRK) pin of each GPU so as to start a frequency reduction operation of each GPU. It can be seen that, in the present application, an underlying hardware circuit is directly used for implementation with relatively quick responses and without intervention of an operating system, whereby the whole frequency reduction operation of the GPU may be completed within 5 ms, and the PSU is prevented from triggering overpower protection within relatively short time. Therefore, loss of service data of a user caused by an exceptional power failure of the server is avoided.