Patents Assigned to Institute of Materials Research & Engineering
  • Publication number: 20030227255
    Abstract: An OLED device having pillars, wherein the pillars serve to pattern a conductive layer during deposition. The profile of the pillars covers the edges of at least one functional layer to protect it from exposure to potentially deleterious substances.
    Type: Application
    Filed: June 10, 2002
    Publication date: December 11, 2003
    Applicants: Institute of Materials Research and Engineering, Osram Opto Semiconductors GmbH
    Inventors: Mark Auch, Ewald Guenther, Soo Jin Chua
  • Patent number: 6660062
    Abstract: A process is provided for chemically modifying a dual-layer hollow fibre, wherein the fibre comprises a first layer consisting essentially of a polyimide and a second layer consisting essentially of a polymer which is substantially unaffected by the chemical modification process. The process comprises contacting the polyimide layer with a polyamine. In addition, a process is provided for chemically modifying a polyimide membrane in general, using a process which comprises contacting the membrane with an alcoholic solution of an aliphatic-aromatic polyamine.
    Type: Grant
    Filed: May 9, 2002
    Date of Patent: December 9, 2003
    Assignee: Institute of Materials Research and Engineering
    Inventors: Ye Liu, Dong-Fei Li, Rong Wang, Tai-Shung Chung
  • Publication number: 20030209185
    Abstract: The GaN single-crystal substrate 11 in accordance with the present invention has a polished surface subjected to heat treatment for at least 10 minutes at a substrate temperature of at least 1020° C. in a mixed gas atmosphere containing at least an NH3 gas. As a consequence, an atomic rearrangement is effected in the surface of the substrate 11 in which a large number of minute defects are formed by polishing, so as to flatten the surface of the substrate 11. Therefore, the surface of an epitaxial layer 12 formed on the substrate 11 can be made flat.
    Type: Application
    Filed: May 8, 2003
    Publication date: November 13, 2003
    Applicants: SUMITOMO ELECTRIC INDUSTRIES, LTD., INSTITUTE OF MATERIALS RESEARCH & ENGINEERING
    Inventors: Masaki Ueno, Eiryo Takasuka, Soo-Jin Chua, Peng Chen
  • Patent number: 6645885
    Abstract: Indium Nitride (InN) and Indium-rich Indium Gallium Nitride (InGaN) quantum dots embedded in single and multiple InxGa1−xN/InyGa1−yN quantum wells (QWs) are formed by using TMIn and/or Triethylindium (TEIn), Ethyldimethylindium (EDMIn) as antisurfactant during MOCVD growth, wherein the photoluminescence wavelength from these dots ranges from 480 nm to 530 nm. Controlled amounts of TMIn and/or other Indium precursors are important in triggering the formation of dislocation-free QDs, as are the subsequent flows of ammonia and TMIn. This method can be readily used for the growth of the active layers of blue and green light emitting diodes (LEDs).
    Type: Grant
    Filed: September 27, 2001
    Date of Patent: November 11, 2003
    Assignees: The National University of Singapore, Institute of Materials Research & Engineering
    Inventors: Soo Jin Chua, Peng Li, Maosheng Hao, Ji Zhang
  • Patent number: 6638365
    Abstract: A method of preparing a silicon surface for a subsequent processing said such as thermal oxidation, or metal silicide formation, via use of a novel wet chemical clean procedure, has been developed. The novel wet chemical clean procedure is comprised of three specific stages, with the first stage featuring the removal of organic contaminants and the growth of a native oxide layer on the silicon surface. A second stage features removal of the native oxide layer and removal of metallic contaminants from the silicon surface, while the third stage is used to dry the silicon surface. The novel wet chemical clean procedure is performed in less time, and using less chemicals, then counterpart wet chemical cleans also used for the preparation of silicon surfaces for subsequent processing steps.
    Type: Grant
    Filed: October 9, 2001
    Date of Patent: October 28, 2003
    Assignees: Chartered Semiconductor Manufacturing Ltd., Institute of Materials Research and Engineering
    Inventors: Jianhui Ye, Simon Chooi, Alex See
  • Patent number: 6531396
    Abstract: A method of fabricating a silicide layer on a silicon region of a semiconductor structure, the method comprising the steps of: providing a semiconductor structure having at least one silicon region on a surface thereof; depositing a layer comprising nickel and platinum on the at least one silicon layer; annealing the semiconductor structure and the nickel/platinum layer to react the nickel and the platinum with underlying silicon to form a nickel-platinum silicide, wherein annealing step takes place at temperature of between 680° C. and 720° C.
    Type: Grant
    Filed: November 17, 2000
    Date of Patent: March 11, 2003
    Assignee: Institute of Materials Research and Engineering
    Inventors: Dongzhi Chi, Syamal Kumar Lahiri, Dominique Mangelinck
  • Publication number: 20020102745
    Abstract: A method of modifying a chip assembly substrate comprising the steps of:
    Type: Application
    Filed: August 2, 2001
    Publication date: August 1, 2002
    Applicant: Institute of Materials Research & Engineering
    Inventors: Syamal Kumar Lahiri, Harvey Monroe Phillips
  • Publication number: 20020076497
    Abstract: A method of plating an aromatic polymer substrate comprises: applying a strippable coating of a non-aromatic polymer to a substrate surface to be plated; selectively illuminating the coated substrate surface with laser light to ablate a selected area of the strippable coating and to activate an underlying region of the substrate surface exposed by the ablation of the strippable coating; contacting the substrate surface with a seeding solution containing polymer-stabilized catalytic seeding particles, so that the seeding particles adhere preferentially to the activated region of the substrate; and electrolessly plating the substrate surface, whereby the seeded areas of the substrate surface are selectively plated.
    Type: Application
    Filed: December 18, 2001
    Publication date: June 20, 2002
    Applicant: INSTITUTE OF MATERIALS RESEARCH AND ENGINEERING
    Inventors: William T. Chen, Peter M. Moran, Harvey M. Phillips
  • Patent number: 6320194
    Abstract: A detachable, portable SEM column that is easily disconnected from the electron gun assembly and specimen chamber of the system, allowing different column designs to be used in a given SEM system. As an alternate design, the electron gun and column are configured as a single detachable, portable assembly. The column of the present invention contains a condenser lens and an objective lens, both designed employing permanent magnet elements for primary field generation. Relatively small coils are used for scanning and precise adjustment of focus.
    Type: Grant
    Filed: May 2, 2000
    Date of Patent: November 20, 2001
    Assignee: Institute of Materials Research and Engineering
    Inventors: Anjam Khursheed, Jacob Chee Hong Phang, John Thiam Leong Thong
  • Patent number: 6287884
    Abstract: A buried hetero-structure with native oxidized current blocking layer for InP-based opto-electronic devices comprises a InP semiconductor substrate, a buffer layer, a ridge mesa containing lower confinement layer, active layer and upper grating confinement layer, a first InP cladding layer and a native oxidized Al-bearing layer as current blocking layers at both lateral edges, a second InP cladding layer, contact layer, contact metal, and the second ridge mesa covered with insulating layer. This method is to facilitate the processing of conventional buried hetero-structure InP-based opto-electronic device and improve the performance under high temperature and high current operation.
    Type: Grant
    Filed: January 20, 1999
    Date of Patent: September 11, 2001
    Assignee: Institute of Materials Research and Engineering
    Inventors: Wang Zhi Jie, Chua Soo Jin
  • Patent number: 6287122
    Abstract: A fiber-reinforced composite material with graded stiffness, and method of making the same. The degree of stiffness variation may be controlled via modifications to the fabrication processes. Products with varying stiffness along their lengths are described. In one example, a dental post is fabricated from material according to the present invention which has one end with low stiffness adapted for insertion into the root of the tooth, and a high stiffness end suitable to support the restoration.
    Type: Grant
    Filed: April 14, 1999
    Date of Patent: September 11, 2001
    Assignee: Institute of Materials Research & Engineering and National University of Singapore
    Inventors: Ramakrishna Seeram, Ganesh Vijay Kumar, Teoh Swee Hin, Loh Poey Ling, Chew Chong Lin
  • Patent number: 6214642
    Abstract: An area array flip chip device produced using wire bonding technology. The design and process for producing such a flip chip involves stud bumps which are bonded on the substrate, to give good electrical interconnections between the chip pads and the substrate pads. This completely eliminates the limitation of not being able to have stud bump interconnections over the active area of the chip, and allows the stud bump interconnection method to be applied over the entire chip area. The design and process can also be applied to the joining of a substrate or first level packaging to the board. In this embodiment, the stud bump process acts as a replacement for the BGA process.
    Type: Grant
    Filed: November 4, 1998
    Date of Patent: April 10, 2001
    Assignee: Institute of Materials Research and Engineering
    Inventors: William T. Chen, Syamal Kumar Lahiri
  • Patent number: 6181097
    Abstract: The present invention provides a high precision three-dimensional alignment system using SPM techniques and method of using the same. The system comprises a fine distance control unit for the effective three-dimensional micromovement in the nanometer range of a planar object, and proximity detection unit to monitor the alignment process. In the preferred embodiment, the fine distance control unit comprises a set of at least three strategically positioned fine distance control elements which are capable of controlled expansion and contraction in the nanometer range. The most preferred embodiment of the fine distance control element comprises a piezoelectric tube, which crystal size may be varied by varying an applied voltage. This system may be applied to microlithography, in which case the planar object is a scribing tool having a planar base with multiple tips fabricated on one surface.
    Type: Grant
    Filed: February 11, 1999
    Date of Patent: January 30, 2001
    Assignee: Institute of Materials Research and Engineering
    Inventors: Sam Fong Yau Li, Hou Tee Ng
  • Patent number: 6057553
    Abstract: A detachable, portable SEM column that is easily disconnected from the electron gun assembly and specimen chamber of the system, allowing different column designs to be used in a given SEM system. As an alternate design, the electron gun and column are configured as a single detachable, portable assembly. The column of the present invention contains a condenser lens and an objective lens, both designed employing permanent magnet elements for primary field generation. Relatively small coils are used for scanning and precise adjustment of focus.
    Type: Grant
    Filed: January 30, 1998
    Date of Patent: May 2, 2000
    Assignee: Institute of Materials Research & Engineering
    Inventors: Anjam Khursheed, Jacob Chee Hong Phang, John Thiam Leong Thong