Abstract: A method of manufacturing three-dimensional semiconductor device includes the steps of: forming a stack structure of a plurality of a first material layers and a second material layers on a substrate in the memory cell region; etching the stack structure to form a plurality of trenches; forming channel layers in the plurality of trenches; and reducing the surface roughness and the interface state by performing annealing treatment to at least one surface of the channel layers.

Abstract: A method of manufacturing a semiconductor device, comprising the steps of: forming a gate dielectric layer and a first amorphous channel layer on a substrate; thinning the first amorphous channel layer; etching the first amorphous channel layer and the gate dielectric layer until the substrate is exposed; forming a second amorphous channel layer on the first amorphous channel layer and the substrate; annealing such that the first amorphous channel layer and the second amorphous channel layer are converted into a polycrystalline channel layer; and thinning the polycrystalline channel layer. According to the method of manufacturing semiconductor device of the present invention, the grain size of the polycrystalline thin film is increased by depositing a thick amorphous film and then annealing and thinning it.

Abstract: A method for manufacturing three-dimensional memory, comprising the steps of: forming a stack structure composed of a plurality of first material layers and a plurality of second material layers on a substrate; etching the stack structure to expose the substrate, forming a plurality of first vertical openings; forming a filling layer in each of the first openings; etching the stack structure around each of the first openings to expose the substrate, forming a plurality of second vertical openings; forming a vertical channel layer and a drain in each of the second openings; removing the filling layer by selective etching, re-exposing the first openings; partially or completely removing the second material layers by lateral etching, leaving a plurality of recesses; forming a plurality of gate stack structure in the recesses; forming a plurality of common sources on and/or in the substrate at the bottom of each of the first openings.

Abstract: There are provided a nanometer semiconductor device with a high-quality epitaxial layer and a method of manufacturing the same. According to an embodiment, the semiconductor device may include: a substrate; at least one nanowire spaced apart from the substrate; at least one semiconductor layer, each formed around a periphery of respective one of the at least one nanowire to at least partially surround the corresponding nanowire, wherein the semiconductor layer(s) formed around the respective nanowire(s) are separated from each other; an isolation layer formed on the substrate, exposing the at least one semiconductor layer; and a gate stack formed on the isolation layer and intersecting the at least one semiconductor layer, wherein the gate stack includes a gate dielectric layer at least partially surrounding a periphery of respective one of the at least one semiconductor layer and a gate conductor layer.

Abstract: There are provided an Integrated Circuit (IC) unit, a method of manufacturing the same, and an electronic device including the IC unit. According to an embodiment, the IC unit includes a first source/drain layer, a channel layer and a second source/drain layer for a first device and a first source/drain layer, a channel layer and a second source/drain layer for a second device stacked in sequence on a substrate. In the first device, the channel layer includes a first portion and a second portion separated from each other. The first source/rain layer and the second source/drain layer each extend integrally to overlap both the first portion and the second portion of the channel layer. The IC unit further includes a first gate stack surrounding a periphery of the first portion and also a periphery of the second portion of the channel layer of the first device, and a second gate stack surrounding a periphery of the channel layer of the second device.

Abstract: A 3-D semiconductor device comprising a plurality of memory cells and a plurality of selection transistors, each of said plurality of memory cells comprises: a channel layer, distributed along a direction perpendicular to the substrate surface; a plurality of inter-layer insulating layers and a plurality of gate stack structures, alternately laminating along the sidewall of the channel layer; a plurality of floating gates, located between the plurality of inter-layer insulating layers and the sidewall of the channel layer; a plurality of drains, located at the top of the channel layer; and a plurality of sources, located in the said substrate between two adjacent memory cells of the said plurality of memory cells.

Abstract: The present disclosure relates to the field of semiconductor Integrated Circuit (IC) manufacture, and provides an InGaAs-based double-gate PMOS Field Effect Transistor (FET). The FET includes a bottom gate electrode, a bottom gate dielectric layer, a bottom gate interface control layer, an InGaAs channel layer, an upper interface control layer, a highly doped P-type GaAs layer, an ohmic contact layer, source/drain metal electrodes, a top gate dielectric layer and a top gate electrode. The source/drain metal electrodes are located on opposite sides of the ohmic contact layer. A gate trench structure is etched to an upper surface of the interface control layer between the source and drain metal electrodes. The top gate dielectric layer uniformly covers an inner surface of the gate trench structure, and the top gate electrode is provided on the top gate dielectric layer.

Abstract: A method for manufacturing a low interface state device includes performing a remote plasma surface process on a III-Nitride layer on a substrate; transferring the processed substrate to a deposition cavity via an oxygen-free transferring system; and depositing on the processed substrate in the deposition cavity. The deposition may be low pressure chemical vapor deposition (LPCVD). The interface state between a surface dielectric and III-Nitride material may be significantly decreased by integrating a low impairment remote plasma surface process and LPCVD.

Abstract: A semiconductor device structure is provided. The semiconductor device includes a semiconductor substrate, a first device, and a second device. Each of the first and second devices includes a gate extending in a first direction, source/drain regions respectively formed on opposite first and second sides of the gate, dielectric spacers formed respectively on outer sidewalls of the gate on the first side and the second side, and conductive spacers serving contacts to the source/drain regions and formed respectively on outer sidewalls of the respective gate spacers. A second direction from the source/drain region on the first side to the source/drain region on the second side crosses the first direction.

Abstract: A method for improving endurance of 3D integrated resistive switching memory, comprising: Step 1: Calculating the temperature distribution in the integrated array by the 3D Fourier heat conduction equation; Step 2, selecting heat transfer mode; Step 3: selecting an appropriate array structure; Step 4: analyzing the influence of integration degree on temperature in the array; Step 5: evaluating the endurance performance in the array; and Step 6: changing the array parameters according to the evaluation result to improve the endurance performance. According to the method of the present invention, based on the thermal transmission mode in the 3D integrated resistive switching device, a suitable 3D integrated array is selected to analyze the influence of the integration degree on the device temperature so as to evaluate and improve the endurance of the 3D integrated resistive switching device.

Abstract: A method for evaluating the thermal effects of 3D RRAM arrays and reducing thermal crosstalk, including the following steps: Step 1: calculating the temperature distribution in the array through 3D Fourier heat conduction equation; Step 2, selecting a heat transfer mode; Step 3, selecting an appropriate array structure; Step 4, analyzing the effect of position of programming device in the array on the temperature; Step 5, analyzing the thermal crosstalk effect in the array; Step 6, evaluating thermal effects and thermal crosstalk; Step 7, changing the array structure or modify operating parameters based on the evaluation results to reduce the thermal crosstalk.

Abstract: An FinFET and a method for manufacturing the same are disclosed. The FinFET comprises: a semiconductor substrate; a stress layer on the semiconductor substrate; a semiconductor fin on the stress layer, the semiconductor fin having two sidewalls extending in its length direction; a gate dielectric on the sidewalls of the semiconductor fin; a gate conductor on the gate dielectric; and a source region and a drain region at two ends of the semiconductor fin, wherein the stress layer extends below and in parallel with the semiconductor fin, and applies stress to the semiconductor fin in the length direction of the semiconductor fin.

Abstract: Provided are a CMOS device having a charged punch-through stopper (PTS) layer to reduce punch-through and a method of manufacturing the same. In an embodiment, the CMOS semiconductor device includes an n-type device and a p-type device. The n-type device and the p-type device each may include: a fin structure formed on a substrate; an isolation layer formed on the substrate, wherein a portion of the fin structure above the isolation layer acts as a fin of the n-type device or the p-type device; a charged PTS layer formed on side walls of a portion of the fin structure beneath the fin; and a gate stack formed on the isolation layer and intersecting the fin. For the n-type device, the PTS layer has net negative charges, and for the p-type device, the PTS layer has net positive charges.

Abstract: There are provided a semiconductor arrangement, a method of manufacturing the same, and an electronic device including the semiconductor arrangement. According to an embodiment, the semiconductor arrangement may include a first semiconductor device and a second semiconductor device stacked in sequence on a substrate. Each of the first semiconductor device and the second semiconductor device may include a first source/drain layer, a channel layer and a second source/drain layer stacked in sequence, and a gate stack surrounding a periphery of the channel layer. The channel layer may comprise a semiconductor material different from that of the first source/drain layer and from that of the second source/drain layer.

Abstract: A planarization process is disclosed. The method includes forming a trench in an area of a material layer which has a relatively high loading condition for sputtering. The method further includes sputtering the material layer to make the material layer flat.

Abstract: Provided are P type MOSFETs and methods for manufacturing the same. The method may include forming source/drain regions in a semiconductor substrate; forming an interfacial oxide layer on the semiconductor substrate; forming a high K gate dielectric layer on the interfacial oxide layer; forming a first metal gate layer on the high K gate dielectric layer; implanting dopants into the first metal gate layer through conformal doping; and performing annealing to change an effective work function of a gate stack including the first metal gate layer, the high K gate dielectric, and the interfacial oxide layer.

Abstract: An N-type MOSFET and a method for manufacturing the same are disclosed. In one aspect, the method comprises forming source/drain regions in a semiconductor substrate. The method also includes forming an interfacial oxide layer on the semiconductor substrate. The method also includes forming a high-k gate dielectric layer on the interfacial oxide layer. The method also includes forming a first metal gate layer on the high-k gate dielectric layer. The method also includes implanting dopants into the first metal gate layer through conformal doping. The method also includes annealing a gate stack to change an effective work function of the gate stack which includes the first metal gate layer, the high-k gate dielectric, and the interfacial oxide layer.

Abstract: There is disclosed a method for manufacturing a semiconductor device comprising two opposite types of MOSFETs formed on one semiconductor substrate, the method comprising: forming a portion of the MOSFET on the semiconductor substrate, said portion of said MOSFET comprising source/drains regions located in the semiconductor substrate, a dummy gate stack located between the source/drain region and above the semiconductor substrate and a gate spacer surrounding the dummy gate stack; removing the dummy gate stack of said MOSFET to form a gate opening which exposes the surface of the semiconductor substrate; forming an interfacial oxide layer on the exposed surface of the semiconductor structure; forming a high-K gate dielectric on the interfacial oxide layer within the gate opening; forming a first metal gate layer on the high-K gate dielectric; implanting doping ions in the first metal gate layer; forming a second metal gate layer on the first metal gate layer to fill up the gate opening; and annealing to diffu

Abstract: Methods of manufacturing stacked nanowires MOS transistors are disclosed. In one aspect, the method includes forming a plurality of fins along a first direction on a substrate. The method also includes forming stack of nanowires constituted of a plurality of nanowires in each of the fins. The method also includes forming a gate stack along a second direction in the stack of nanowires, the gate stack surrounding the stack of nanowires. The method also includes forming source/drain regions at both sides of the gate stack, the nanowires between the respective source/drain regions constituting a channel region. A stack of nanowires may be formed by a plurality of etching back, laterally etching a trench and filling the trench. The laterally etching process includes isotropic dry etching having an internally tangent and lateral etching, and a wet etching which selectively etches along respective crystallographic directions.

Abstract: A nonvolatile resistive switching memory includes an inert metal electrode, a resistive switching functional layer, and an easily oxidizable metal electrode. A graphene intercalation layer with nanopores, interposed between the easily oxidizable metal electrode and the resistive switching functional layer, is capable of controlling the metal ions, which are formed by the oxidation of the easily oxidizable metal electrode during the programming of the device, and only enter into the resistive switching functional layer through the position of the nanopores. Further, the graphene intercalation layer with nanopores is capable of blocking the diffusion of the metal ions, making the metal ions, which are formed after the oxidation of the easily oxidizable metal electrode, enter into the resistive switching functional layer only through the position of the nanopores during the programming of the device, thereby controlling the growing position of conductive filament.