Abstract: Exemplary embodiments of the present disclosure provide a spin valve and a spintronic device comprising the same. The spin valves may comprise two or more magnetic layers stacked in sequence, wherein any two adjacent magnetic layers among the two or more magnetic layers have different coercive forces, and at least one of the any two adjacent magnetic layers is a van der Waals magnetic layer, wherein the van der Waals magnetic layer refers to a magnetic layer made of a van der Waals magnetic material.

Abstract: Embodiments of the present disclosure disclose an optoelectronic oscillator including an optical chip and a microwave chip. The optical chip is implemented by fabricating different optoelectronic devices on an integrated optical substrate, comprising: a laser assembly; a mode selection device coupled to the laser assembly, and configured to receive the laser and perform mode selection; an optical delay module coupled to the mode selection device; and a detector coupled to the optical delay module. The microwave chip is a microwave integrated circuit formed by fabricating microwave elements on a semiconductor substrate, comprising: a microwave processing circuit configured to receive microwave signal and perform signal processing; a coupler coupled to the microwave processing circuit, and configured to provide a part of the microwave signal to a phase shifter and output the other part thereof; and a phase shifter configured to feed the phase-shifted microwave signal to the laser assembly.

Abstract: A voltage controlled magnetic random memory unit, a memory, and a logic device thereof. The memory unit includes: a ferroelectric layer applied with a first positive or negative voltage to control a directional switching of magnetization; a spin-orbit coupling layer located above the ferroelectric layer and applied with a second voltage to produce a spin current in a direction perpendicular to the spin-orbit coupling layer; a first magnetic layer located above the spin-orbit coupling layer, wherein, the spin current induces a random up and down magnetic switching of the first magnetic layer. The spin current may induce a directional switching of the first magnetic layer in conjunction with the first voltage applied to the ferroelectric layer.

Abstract: An InGaN-based resonant cavity enhanced detector chip based on porous DBR, including: a substrate (10); a buffer layer (11) formed on the substrate (10); a bottom porous DBR layer (12) formed on the buffer layer (11); an n-type GaN layer (13) formed on the bottom porous DBR layer (12), wherein one side of the n-type GaN layer (13) is recessed downward to form a mesa (13?), and the other side of the n-type GaN layer (13) is protruded; an active region (14) formed on the n-type GaN layer (13); a p-type GaN layer (15) formed on the active region (14); a sidewall passivation layer (20) formed on an upper surface of the p-type GaN layer (15) and sidewalls of the protruded n-type GaN layer (13), the active region (14), and the p-type GaN layer (15), wherein the sidewall passivation layer (20) on the upper surface of the p-type GaN layer (15) has a window in a middle; a transparent conductive layer (16) formed on the sidewall passivation layer (20) and the p-type GaN layer (15) at the window; an n-type electrode (18

Abstract: A GaN-based VCSEL chip based on porous DBR and a manufacturing method of the same, wherein the chip includes: a substrate; a buffer layer formed on the substrate; a bottom porous DBR layer formed on the buffer layer; an n-type doped GaN layer formed on the bottom porous DBR layer, which is etched downward on its periphery to form a mesa; an active layer formed on the n-type doped GaN layer; an electron blocking layer formed on the active layer; a p-type doped GaN layer formed on the electron blocking layer; a current limiting layer formed on the p-type doped GaN layer with a current window formed at a center thereof, wherein the current limiting layer covers sidewalls of the active layer, the electron blocking layer and the convex portion of the n-type doped GaN layer; a transparent electrode formed on the p-type doped GaN layer; an n-electrode formed on the mesa of the n-type doped GaN layer; a p-electrode formed on the transparent electrode with a recess formed therein; and a dielectric DBR layer formed on

Abstract: A multi-band channel encrypting switch control device is provided. The device comprises a transmission part and a receiving part. The transmission part comprises: a first controller to store a secret key and to send a digital signal; an encrypting unit to encrypt the digital signal; a multi-band transmitter to select a plurality of wavebands to transmit the encrypted signal on the plurality of wavebands under control of the secret key; and a switch. The receiving part comprises: a multi-band detector to receive the encrypted signal transmitted on the plurality of wavebands; a decrypting unit to decrypt the encrypted signal; and a second controller to store the secret key and to decide whether or not to issue a switch signal by processing the signal and making decisions using the process result. A transmission device, a receiving device, and a control method are also provided.

Abstract: An InGaN-based resonant cavity enhanced detector chip based on porous DBR, including: a substrate (10); a buffer layer (11) formed on the substrate (10); a bottom porous DBR layer (12) formed on the buffer layer (11); an n-type GaN layer (13) formed on the bottom porous DBR layer (12), wherein one side of the n-type GaN layer (13) is recessed downward to form a mesa (13?), and the other side of the n-type GaN layer (13) is protruded; an active region (14) formed on the n-type GaN layer (13); a p-type GaN layer (15) formed on the active region (14); a sidewall passivation layer (20) formed on an upper surface of the p-type GaN layer (15) and sidewalls of the protruded n-type GaN layer (13), the active region (14), and the p-type GaN layer (15), wherein the sidewall passivation layer (20) on the upper surface of the p-type GaN layer (15) has a window in a middle; a transparent conductive layer (16) formed on the sidewall passivation layer (20) and the p-type GaN layer (15) at the window; an n-type electrode (18

Abstract: An ultraviolet laser 3D printing device includes a thermostat, a laser head, a non-contact type temperature monitoring device, a scanning galvanometer, a processing platform, a powder laying device, a material to be processed, a computer control system. The device is configured to perform the following functions: presetting a processing temperature by the control system; during the processing procedure, the temperature rise condition of the processed object is monitored by the non-contact type temperature monitoring device and fed back in real time to the control system; and by recording the rise value of the temperature within a certain period, the system can obtain the absorption capability of the laser and the temperature rise degree of the processed material, so that the laser output power can be calculated according to the preset processing temperature value, and the laser power can be adjusted in real time to precisely control the processing temperature.

Abstract: A wireless radio-frequency transmission apparatus includes a phase frequency detector, a charge pump, a loop filter and a twin voltage-controlled oscillator. The twin voltage-controlled oscillator includes a first oscillator and a second oscillator. When the twin voltage-controlled oscillator is in a reception mode, the first and the second oscillators are coupled to each other to form a quadrature voltage-controlled oscillator, and the quadrature voltage-controlled oscillator, the phase frequency detector, the charge pump and the loop filter constitute a phase-locked loop to generate quadrature carriers. When the twin voltage-controlled oscillator is in a transmission mode, the first oscillator, the phase frequency detector, the charge pump and the loop filter constitute a phase-locked loop, and the second oscillator performs frequency modulation on transmitted data.

Abstract: The present invention discloses a semiconductor laser comprising an optical waveguide structure which may include a lower waveguide layer, an active layer of multiple quantum wells and an upper waveguide layer, which are successively stacked from bottom to top, a grating layer being formed on upper portion of the active layer, wherein the upper waveguide layer, a cladding layer and a contact layer are formed as a ridge which has a light incidence end surface and a light output end surface, wherein a beam expanding structure is formed on one end of the output end surface. The beam expanding structure has a beam expanding portion with a shape gradually contracted inwards from the light output end surface. Preferably, the beam expanding portion has a horizontal divergence angle of 5° to 20°.

Abstract: The present disclosure discloses a multi-standard performance reconfigurable I/Q orthogonal carrier generator. The generator may implement a continuously covered I/Q carrier output of 0.1-5 GHz and continuously covered differential signal outputs of 5-10 GHz and 1.5-3 GHz by means of reasonable frequency assignment; also, carrier signals under various frequencies with different loop bandwidths, different phase noises, different power consumption levels and different locking times can be generated by configuring a programmable charge pump (102), a loop filter (103) parameter, a multi-path voltage-controlled oscillator (104) and a first multiplexer (105) corresponding thereto, a five-stage-division-by-two frequency division link (109) and a corresponding second multiplexer (110) and third multiplexer (112), so as to implement generation of a multi-standard performance reconfigurable I/Q orthogonal carrier.

Abstract: The present disclosure provides an analog readout preprocessing circuit for a CMOS image sensor and a control method thereof. The analog readout preprocessing circuit comprises an extended count-type integration cycle-successive approximation hybrid analog-to-digital conversion capacitor network 1 configured to achieve readout and analog-to-digital conversion of signals output from the CMOS image sensor; an operational amplifier configured to utilize “virtual short” of two input terminals of the operational amplifier and the charge conservation principle, to achieve a function of extended count-type integration cycle-successive approximation hybrid analog-to-digital conversion, where the extended count-type integration can effectively reduce a thermal noise and a flicker noise within the image sensor; a comparator configured to compare voltages at two terminals to achieve a function of quantization of signals; and a control signal generator configured to provide control signals.

Abstract: An integral chip is disclosed by embodiments of the present disclosure, including: two mono-mode vertical coupling gratings, two modulation modules, one 2×1 multi-mode interference coupler, and one dual-mode vertical coupling grating. The integral chip is capable of operating in dual wavelengths and dual polarization states by combination of polarization multiplexing and wavelength division multiplexing so as to realize modulation of complex formats and to enhance data modulation rate.

Abstract: The present invention provides a method of aligning a quadrate wafer in a first photolithography process. The method includes: step A: fabricating mask aligning markers in a periphery region of a mask, which is used for a first exposure process of the quadrate wafer, around a mask pattern of the mask; step B: during the first exposure process, positioning the quadrate wafer in a preset region by using the mask aligning markers on the mask, and exposing the quadrate wafer through the mask; and step C: performing alignment for the quadrate wafer during a second exposure process and subsequent exposure processes by using aligning markers on the quadrate wafer that are obtained during the first exposure process. The method may be easily and reliably performed to ensure intact dies at periphery of a quadrate wafer to be produced and thus render increased yield of chips.

Abstract: The present invention proposes a dynamically reconfigurable multi-level parallel single instruction multiple data array processing system which has a pixel level parallel image processing element array and a row-parallel array processor. The PE array mainly implements a linear operation which is adapted to be executed in parallel in the low and middle levels of image processing and the RP array implements an operation which is adapted to execute in row-parallel in the low and middle levels of image processing or more complex nonlinear operations.

Abstract: The present disclosure relates to a light emitting diode packaging structure and the method of manufacturing the same. The light emitting diode packaging structure has an insulating substrate with through holes formed on each side of the upper surface thereof, the through hole being filled with conductive metal. Additionally, a n-type layer, an active layer, a p-type layer, an insulating layer and a p-type electrode are formed on the insulating substrate. The structure further may include a n-type electrode provided on a side of the upper surface of the n-type layer; a first back electrode provided at one side of the back surface of the insulating substrate; a second back electrode provided at the other side of back surface of the insulating substrate; and an optical element packaged on the base substrate.

Abstract: The disclosure provides a system and method for multi-functional online testing of semiconductor light-emitting devices or modules. The system includes an electrical characteristic generating and testing equipment, one or more optical characteristic detecting and controlling equipments, an optical signal processing and analyzing equipment, one or more thermal characteristic detecting equipments, a central monitoring and processing computer, a multi-channel integrated drive controlling equipment, one or more multi-stress accelerated degradation controlling equipments, and one or more load boards. The present disclosure enables in-situ online monitoring and testing under accelerated degradation in a multi-stress accelerated degradation environment.

Abstract: A 3D package device of a photonic integrated chip matching circuit, comprising: a first carrier substrate; a first microwave transmission line array formed by evaporation on the top surface of the first carrier substrate to provide bias voltages and high-frequency modulation signals to the photonic integrated chip; a second carrier substrate formed perpendicularly to the first carrier substrate or to have a certain angle with respect to the first carrier substrate, so as to constitute a 3D structure; a second microwave transmission line array formed by evaporation on the bottom surface of the second carrier substrate to match electrodes of the first microwave transmission line array, the second microwave transmission line array being soldered or sintered with the electrodes of the first microwave transmission line array; an electrode array formed by evaporation on a side surface or two opposite side surfaces of the second carrier substrate; and a microwave circuit.

Abstract: A method can include: growing a Ge layer on a Si substrate; growing a low-temperature nucleation GaAs layer, a high-temperature GaAs layer, a semi-insulating InGaP layer and a GaAs cap layer sequentially on the Ge layer after a first annealing, forming a sample; polishing the sample's GaAs cap layer, and growing an nMOSFET structure after a second annealing on the sample; performing selective ICP etching on a surface of the nMOSFET structure to form a groove, and growing a SiO2 layer in the groove and the surface of the nMOSFET structure using PECVD; performing the ICP etching again to etch the SiO2 layer till the Ge layer, forming a trench; cleaning the sample and growing a Ge nucleation layer and a Ge top layer in the trench by UHVCVD; polishing the Ge top layer and removing a part of the SiO2 layer on the nMOSFET structure; performing a CMOS process.

Abstract: A method can include: growing a Ge layer on a Si substrate; growing a low-temperature nucleation GaAs layer, a high-temperature GaAs layer, a semi-insulating InGaP layer and a GaAs cap layer sequentially on the Ge layer after a first annealing, forming a sample; polishing the sample's GaAs cap layer, and growing an nMOSFET structure after a second annealing on the sample; performing selective ICP etching on a surface of the nMOSFET structure to form a groove, and growing a SiO2 layer in the groove and the surface of the nMOSFET structure using PECVD; performing the ICP etching again to etch the SiO2 layer till the Ge layer, forming a trench; cleaning the sample and growing a Ge nucleation layer and a Ge top layer in the trench by UHVCVD; polishing the Ge top layer and removing a part of the SiO2 layer on the nMOSFET structure; performing a CMOS process.