Abstract: Disclosed herein are methods and systems for sensing and controlling the temperature of a resistive element configured for use in a read/write head of a magnetic data storage device. In one embodiment, a method includes detecting a voltage across the resistive element, where the voltage varies as a function of a temperature of the resistive element. The method also includes comparing the voltage to a predetermined value to determine a variation of the voltage from the predetermined value, and then altering a power applied to the resistive element based on the variation. In this exemplary embodiment, the temperature of the resistive element is then controlled as a function of the altered applied power.

Abstract: A method of operating a memory circuit having a plurality of blocks of memory cells (400–404) is disclosed. The method includes storing data in the plurality of blocks of memory cells. A first block of memory cells (400) is selected in response to a first address signal (RAY0). A row of memory cells (430–436) in the first block of memory cells is selected in response to a second address signal (RAX0). A first voltage is applied to a first power supply terminal (412) of the first block of memory cells in response to the first address signal. A second voltage different from the first voltage is applied to a first power supply terminal (412) of another block of memory cells (402) of the plurality of blocks of memory cells. Data is retained in the other block of memory cells.

Abstract: In a wireless communication receiver (31) of a wireless communication system that utilizes transmit diversity and turbo coding, symbol decisions are based at least in part on a posteriori probabilities (47, 48) produced by SISO decoders (35, 36). These probabilities are produced iteratively in alternating fashion to support the symbol decision process. The SISO decoder associated with the weakest (92) wireless communication channel goes first (93) in the iterative process.

Abstract: An etching method that uses an etch reactant retained within at least a semi-solid media (120, 220, 224, 230). The etch reactant media is applied to selectively etch a surface layer (106, 218, 222). The etch reactant media may be applied to remove metal shorts (222), smearing and eaves resulting from CMP or in failure analysis for uniform removal of a metal layer (218) without damaging the vias, contact, or underlying structures.

Abstract: A fan control system and method that maintains the operating temperature of computer and electronic devices or components at about a predetermined control level to minimize power consumption and audible noise. The fan control system is a programmable closed loop system including a temperature sensor, first and second fan controllers, and a fan/motor assembly including a power converter, a motor, and a fan. The first fan controller provides programmable acceleration/deceleration of the fan during an initial fan spin up, and the second fan controller runs the fan only as fast as necessary to keep the sensed temperature level of a computer device as close as possible to the predetermined control level, thereby minimizing the power consumption of the system and the audible noise of the fan.

Abstract: Narrowband interference can seriously degrade the overall performance of a communications network without significantly damaging a large percentage of the communications network's transmissions. In a single tone communications network, narrowband interference can reduce the overall signal-to-noise ratio to a level such that a receiver can no longer accurately decode the received transmission. However, the receiver's filters and equalizers often can filter out the effects of the narrowband interference and the receiver can accurately decode the received transmission if the receiver can restart the decoding at the point when the narrowband interference began interfering with the transmission. A technique using sequential decoding with backtracking and adaptive equalization permits the receiver to adapt to the presence of the narrowband interference and backtrack the decoding to a point prior to the interference.

Abstract: The present invention provides, in one embodiment, a gate structure (100). The gate structure comprises a gate dielectric (105) and a gate (110). The gate dielectric includes a refractory metal and is located over a semiconductor substrate (115). The semiconductor substrate has a conduction band and a valence band. The gate is located over the gate dielectric and includes the refractory metal. The gate has a work function aligned toward the conduction band or the valence band. Other embodiments include an alternative gate structure (200), a method of forming a gate structure (300) for a semiconductor device (301) and a dual gate integrated circuit (400).

Abstract: A multi-path equalization system for orthogonal frequency division multiplexing communication (OFDM) system includes a first estimator for estimating the channel characteristic using pilot signal. A divider is coupled to the estimator for dividing each sub-carrier with the channel characteristic to get the equalization to the data signal. A de-mapper uses the phase and amplitude correction of the channel estimate to recover the data signals. An improved channel estimation is provided by a repeat channel estimation feedback loop that includes the de-mapper a multiplier, an inverse fast Fourier transform (IFFT), a low pass filter and a fast Fourier transform (FFT). The improved channel estimation is obtained by multiplying at the multiplier the conjugate of the de-mapped data to the input sub-carriers and applying inverse FFT, low pass filtering and FFT to get the new channel estimate. Each sub-carrier is divided with new channel characteristic to get new equalization to the data signal.

Abstract: A capping layer (118) is used during an anneal to form fully silicided NiSi gate electrodes (120). The capping layer (118) comprises a material with an affinity for boron, such as TiN. The capping layer (118) serves as a boron trap that reduces the interface boron concentration for PMOS transistors without reducing the interface arsenic concentration for NMOS transistors.

Abstract: While the manufacturing of integrated circuits (IC) has become a mostly automated process, the loading of the ICs into storage and shipping tubes 105 still requires a large amount of human interaction. A major stumbling block to the automation is the removal and insertion of retention pins 115 in the tubes. The present invention uses pressurized air 406 to hold a partially extracted retention pin 115 in position while the tube 105 is loaded. Once loaded, the retention pin 115 is reinserted. By not fully extracting the retention pin 115, alignment is maintained, simplifying the reinsertion step.

Abstract: An aspect of the present invention provides multiple switches in a transceiver, which enable pins provided for transmission and reception to be connected to either a transmit port or a receive port, as desired during operation. As a result, the transceiver can be auto-configured to connect the specific pin, on which signals are being received, to the receive port. Similarly, the transceiver can be auto-configured to connect the specific pin, on which the signals need to be transmitted, to the transmit port. Various design considerations in providing such switches are also described.

Abstract: Methods are disclosed for semiconductor device fabrication in which dopants are selectively implanted into transistor gate structures to counteract or compensate for dopant depletion during subsequent fabrication processing. A patterned implant mask is formed over a semiconductor device, which exposes at least a portion of the gate structure and covers the remaining upper surfaces of the device. Thereafter, dopants are selectively implanted into the exposed gate structure.

Abstract: An arrangement provides a reduced harmonic content output signal that represents a value of a digital input signal. The arrangement includes plural storage devices 301 . . . configured to sample and store the digital input signal at different respective phases of a clock signal. The arrangement also has plural current steering digital-to-analog converters (DACs) 311 . . . configured to receive respective stored digital signals from respective ones of the plural storage devices, and to provide respective currents that represent the received stored digital signals. The arrangement also includes a combining arrangement configured to combine the currents from respective ones of the plural current steering DACs, so as to provide the reduced harmonic content output signal that represents the value of the digital input signal.

Abstract: A digital device 310 with a plurality of collocated wireless networks encounters inter-network interference if the collocated wireless networks operate in a common operating frequency. A coordinator unit 510, coupled to the plurality of wireless networks, provides a transmission reservation system wherein a wireless network with a need to transmit can request and receive a reservation for time to transmit. The coordinator unit 510 provides a way to schedule transmissions from the plurality of wireless networks and to reduce the probability of collisions.

Abstract: A method of tracing data processor activity with recover from detection of trace stream corruption. If the first trace data following detection of corruption is not a program counter sync point, then the trace transmits an indication of the current program counter address in an offset format from the program counter address of a last transmitted program counter sync point and then transmits trace data in event offset format. If the first trace data following detection of corruption is a program counter sync point, then the trace transmits trace data in event offset format.

Abstract: A tri-value decoder and method for decoding at least three states of an input signal are provided. An exemplary tri-value decoder and method can facilitate decoding of input signals without the use of threshold values and/or forcing a tri-state input signal to a mid-rail value for tri-state detection, and with less dependence on variations in product, process and temperature. In accordance with an exemplary embodiment, an exemplary tri-value decoder circuit comprises a switch circuit, a feedback loop and a sequence detector. An exemplary switch circuit is configured to facilitate sampling of a tri-state input signal through control by the feedback loop, with the sequence detector configured for decoding the tri-state input signal into a two-bit digital signal by detecting at least two samples of the tri-state input signal during a sampling period.

Abstract: The present invention provides, in one embodiment, a method of fabricating a semiconductor device (100). In one embodiment, the method includes growing an oxide layer 120 from a substrate 104, 106 over a first dopant region 122 and a second dopant region 128, implanting a first dopant through the oxide layer 120, into the substrate 104 in the first dopant region 122, and adjacent a gate structure 114, and substantially removing the oxide layer 120 from the substrate within the second dopant region 128. Subsequent to the removal of the oxide layer 120 in the second dopant region 128, a second dopant that is opposite in type to the first dopant is implanted into the substrate 106 and within the second dopant region 128 and adjacent a gate structure 114.

Abstract: A wireless transmitter (TX1). The transmitter comprises circuitry for providing a plurality of control bits (CONTROL) and circuitry for providing a plurality of user bits (USER). The transmitter further comprises circuitry (16) for modulating the plurality of control bits and the plurality of user bits into a stream of complex symbols and circuitry (18) for converting the stream of complex symbols into a parallel plurality of complex symbol streams. The transmitter further comprises circuitry (20) for performing an inverse fast Fourier transform on the parallel plurality of complex symbol streams to form a parallel plurality of OFDM symbols and circuitry (22) for converting the parallel plurality of OFDM symbols into a serial stream of OFDM symbols. The serial stream consists of an integer N+1 OFDM symbols. Each OFDM symbol in the serial stream of OFDM symbols comprises a plurality of data points. Finally, selected OFDM symbols (SF1.

Abstract: A method of preventing trace data first-in-first-out buffer overflow in a pipelined data processor stops new instructions when a trace data first-in-first-out buffer is in danger of overflowing. The method also stalls a predetermined number of pipeline stages in the pipeline ahead of the first pipeline stage. The trace data first-in-first-out buffer is emptied while the pipeline is stalled. On restart, the stalled pipeline stages are restarted ahead of re-enabling new instructions. Asynchronous trigger events received during the stall may be buffered and unrolled in order or merely stored and applied simultaneously on restart.

Abstract: The present invention provides, in one embodiment, a method of fabricating a semiconductor device (100). In one embodiment, the method includes growing an oxide layer 120 from a substrate 104, 106 over a first dopant region 122 and a second dopant region 128, implanting a first dopant through the oxide layer 120, into the substrate 104 in the first dopant region 122, and adjacent a gate structure 114, and substantially removing the oxide layer 120 from the substrate within the second dopant region 128. Subsequent to the removal of the oxide layer 120 in the second dopant region 128, a second dopant that is opposite in type to the first dopant is implanted into the substrate 106 and within the second dopant region 128 and adjacent a gate structure 114.