Abstract: A self-adaptive graphic equalizer operable to equalize the affects of an audio system on an audio signal includes an adaptive graphic equalizer having a plurality of equalizing filters, where the plurality of equalizing filters have different center frequencies equidistant from one another and spanning a predetermined audio bandwidth. Each equalizing filter is operable to filter an ith sub-band of the audio signal. A plurality of first filters are coupled to the audio system, each first filter is operable to filter an ith sub-band of an output signal of the audio system. A plurality of second filters are operable to filter an ith sub-band of the audio signal. A gain adjuster is operable to adjust the ith sub-band of the adaptive graphic equalizer in response to a difference in the ith sub-band of the filtered output signal from the plurality of first filters and the ith sub-band of the filtered audio signal from the plurality of second filters.

Abstract: A software controlled mechanism causing a test equipment to place the edges of test signals accurately. The mechanism determines expected time of occurrence of an edge of a signal in relation to a tester cycle time. The mechanism sends commands to the test equipment to receive back the signal (of interest) in multiple cycles and provides the time points corresponding to the edge in the multiple cycles. The software controlled mechanism computes an error based on the time points and the expected time, and adjusts the timing of the edges of the signal according to the error. Such computation and adjustment are performed until the error is within an acceptable range.

Abstract: State retention registers for use in low-power standby modes of digital IC operation are provided, wherein: a differential circuit (M1?M3; M1?M4) is used to load the shadow latch from the normal functional latch; the signal (REST, RESTZ) used to restore data from the shadow latch to the normal functional latch is a “don't care” signal while the shadow latch is retaining the data during low-power standby mode; retained data from the shadow latch is restored to the normal functional latch via a transistor gate connected to a node (N10) of the shadow latch where the retained data is provided; a power supply (VDD) other than the shadow latch's power supply (VRETAIN) powers the data restore operation; and the normal functional latch is operable independently of the operational states of the high Vt transistors (M1, M2, M5 and M6; M3, M4, M5 and M6) used to implement the state retention functionality.

Abstract: A positioning driver (32) for a voice coil motor (22) in a disk drive system (10) is disclosed. Pulse-width-modulated prestage drivers (46) are coupled to power transistors (50) arranged in an “H” bridge for driving the voice coil motor (22), biased with a power supply voltage (VM). The pulse-width-modulated prestage drivers (46) drive the power transistors (50) according to a comparison between an error signal from an error amplifier (36) and a ramp clock signal (RMP) generated by a ramp clock generator (46). The ramp clock generator (46) includes a control circuit (68) that modulates the high and low limits of the ramp clock signal (RMP) in response to variations in the power supply voltage (VM). This modulation of the high and low limits compensates for variations in the gain of the power transistors (50) resulting from variations in the power supply voltage (VM).

Abstract: A write driver output circuit having a programmable output impedance. A plurality of amplifiers are disposed in parallel between an input and an output of an impedance matching section of the write driver circuit and can be selectively enabled to correspondingly set the output impedance of the write driver circuit. The amplifiers may be Class AB amplifiers, each of which have a smaller size than an conventional AB used in a single amplifier write driver circuit. Each of the Class AB amplifiers has a corresponding matching resistor, and a current source, each being selectively enabled and disabled by enabling and disabling, respectively, the corresponding current sources, such as through the use of serial interface bits.

Abstract: Memory devices and memory cell groups therefor are disclosed, which comprise series connected ferroelectric (FE) memory cells accessible using a single bitline. The cells individually comprise a transistor and an FE capacitor where a single cell within the group or array is connected to a bitline for external access during read, write, and/or restore operations. Methods are also disclosed for reading target cells in a memory cell group.

Abstract: A system comprising a first double data rate (DDR) memory device, a second DDR memory device coupled to the first DDR memory device, the second DDR memory device not using a delay locked loop (DLL) device to synchronize clock signals. The system further comprises a logic coupled to the first and second DDR memory devices. The logic is adapted to receive data from the first and second DDR memory devices by way of a single conductive pathway.

Abstract: A method and system for reducing the power consumption of a direct memory access (DMA) controller. A preferred method, for example, comprises: queuing a first DMA request in a queue; responding to the first queued DMA request when the computer system resources necessary for a DMA transfer are available; and placing at least some components of the computer system into a reduced power consumption state when the computer system resources necessary for the DMA transfer are not available.

Abstract: A flash memory data structure, a flash memory manager, a flash memory containing the data structure and a method of extending a configuration space of a memory. In one embodiment, the flash memory data structure includes fixed length cells, each having (1) a control and identifier section for containing a unique identifier and (2) a data section for containing a configuration value pertaining to the unique identifier, wherein the unique identifier is dynamically configurable in at least one of the fixed length cells.

Abstract: A method and apparatus for adaptive buffer sizing adjusts the size of the buffer at different levels using a “high water mark” to different levels for different system conditions. The high water mark is used by the buffer logic as an indication of when to assert the buffer “Full” flag. In turn, the full flag is used by the instruction fetch logic as an indication of when to stop fetching further instructions.

Abstract: The present invention provides, in one embodiment, a process for fabricating a metal oxide semiconductor (MOS) device (100). The process includes forming a gate (120) on a substrate (105) and forming a source/drain extension (160) in the substrate (105). Forming the source/drain extension (160) comprises an abnormal-angled dopant implantation (135) and a dopant implantation (145). The abnormal-angled dopant implantation (135) uses a first acceleration energy and tilt angle of greater than about zero degrees. The dopant implantation (145) uses a second acceleration energy that is higher than the first acceleration energy. The process also includes performing an ultrahigh high temperature anneal of the substrate (105), wherein a portion (170) of the source/drain extension (160) is under the gate (120).

Abstract: Contacts are formed to integrated circuit devices by first forming a conductive layer (80) on a semiconductor device. An optional dielectric layer (130) is formed over the conductive layer and a carbon containing dielectric layer (140) is formed over the optional dielectric layer (130). Contacts are formed to the conductive layer (80) by etching openings in the carbon containing dielectric layer (140) and the optional dielectric layer (130).

Abstract: Space time transmit diversity (9, 14, 17, 19) is applied at the block level to an original block of bits (12) in order to reduce the effects of fading in wireless communication systems that use nonlinear modulation schemes (13, 33). At the receiving end, fading parameters (?1, ?2) are estimated (?E1, ?E2) and the properties of complex conjugates are utilized (28, 29, 201, 202) to produce a result (r1, r2) that is representative of the original block of bits.

Abstract: In order to measure the power consumed by a bus in a digital signal processor, each bus conductor has a lead electrically coupled thereto. The lead is coupled to apparatus that provides a signal each time the logic state of the bus is changed. The total number of logic signal changes for a given period of time is determined. Because power is consumed by the bus only during logic state transitions, the total number of logic state transitions can be multiplied by the power consumed by the bus during each transition to provide the total power consumed during a predetermined period of time. The power consumed by the bus during each logic state transition can be determined by simulation or other techniques. The power consumed by the operation of the bus can be further divided into power consumed by the internal (on-chip) bus and the external (off-chip) bus.

Abstract: Systems and methods are provided for performing signal processing on communication data utilizing scale reduced Fast Fourier Transform computations. The present invention provides scaling in a Fast Fourier Transform computation at stages where it is determined that bit growth is present and omits scaling at stages where it is determined that bit growth is absent. The determination is based on the characteristics of the input signal. The determination can be made off-line by modeling and/or simulation or in real-time by analyzing the input signal to determine stages at which bit growth is present and/or absent and setting the stage scaling accordingly.

Abstract: An improved circuit is provided that buffers the output of a DAC while improving the bandwidth and linearity of the circuit. A DAC comprises an output signal of a switched DAC circuit coupled to an inverting node of an output buffer configured as a difference amplifier, while a non-inverting node of the difference amplifier is coupled to a fixed reference potential. As a result, the difference amplifier buffers the output of the switched DAC circuit while permitting the use of N-type input stages in the amplifier, which can enhance the bandwidth capability of the circuit.

Abstract: In one embodiment, a method for extracting C-V characteristics of ultra-thin oxides includes coupling a device under test to a testing structure, in which the device under test includes a plurality of transistors. Alternatively, the device under test includes a plurality of varactors. The method further includes inputting a radio frequency signal of at least one GHz into the testing structure, de-embedding the parasitics of the testing structure, inputting a bias into the device under test, determining the capacitance density per gate width of the device under test, plotting capacitance density per gate width versus gate length to obtain a first curve, and determining a slope of the first curve. These steps are repeated for one or more additional biasing conditions, and the determined slopes are plotted on a capacitance density per voltage graph to obtain a C-V curve for the device under test.

Abstract: An amplifier apparatus includes: (a) an integrator having an input for receiving an input signal, and integrating the input signal to present an integrated signal; (b) a first comparer coupled with the integrator for comparing the integrated signal with a varying reference signal to produce an output signal; and (c) a feedback circuit, coupled to receive the integrated signal and coupled with the input structure, that includes: (1) a second comparer coupled for receiving the integrated signal and comparing the integrated signal with a reference level related to the reference signal; the second comparer presents an actuating signal when the integrated signal has a predetermined relationship with the reference level; and (2) a switch coupled with the second comparer unit and with the input and responding to the actuating signal to affect the input signal appropriately to reduce the integrated signal when the actuating signal is at a predetermined level.

Abstract: A new iterative hierarchical linear regression method for generating a set of linear transforms to adapt HMM speech models to a new environment for improved speech recognition is disclosed. The method determines a new set of linear transforms at an iterative step by Estimate-Maximize (EM) estimation, and then combines the new set of linear transforms with the prior set of linear transforms to form a new merged set of linear transforms. An iterative step may include realignment of adaptation speech data to the adapted HMM models to further improve speech recognition performance.

Abstract: A DC-DC converter circuit includes a transformer with a resonate filter or snubber connected at a primary side and a switch for controlling operation of the converter. A secondary side of the transformer includes self-driven synchronous rectifiers and an output filter. Transistors are provided at the gates leads of the rectifiers and themselves are provided with a fixed voltage at their gates so as to clamp the peak voltages across to the rectifiers.