Patents Assigned to Instruments Incorporated
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Patent number: 8185789Abstract: Scan and Scan-BIST architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure improves upon low power Scan and Scan-BIST methods. The improvement allows the low power Scan and Scan-BIST architectures to achieve a delay test capability equally as effective as the delay test capabilities used in conventional scan and Scan-BIST architectures.Type: GrantFiled: August 4, 2011Date of Patent: May 22, 2012Assignee: Texas Instruments IncorporatedInventors: Lee D. Whetsel, Joel J. Graber
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Patent number: 8184154Abstract: A surveillance method periodically detects an image of the area, identifies and tracks each moving object in a succession of the detected images, detects radio frequency emissions from the area and correlates an identified object with a detected radio frequency emission. The method detects events in the tracking of the moving object. The method stores corresponding data optionally including image data in non-volatile memory upon detection of a combination of an event and a corresponding radio frequency emission. The method triggers an alarm such as an audible alarm, a visual alarm, an email, a short text message or a telephone call detection of a combination of an event and a corresponding radio frequency emission.Type: GrantFiled: February 27, 2007Date of Patent: May 22, 2012Assignee: Texas Instruments IncorporatedInventors: Leonardo W. Estevez, Keith G. Gutierrez
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Patent number: 8183939Abstract: A ring oscillator has at least one latch connected to the outputs of at least one oscillator stage, where the latch drives the outputs of the oscillator stage to opposite states during startup, and drive strength reduction circuitry to reduce drive strength of the latch after startup when the oscillator is oscillating.Type: GrantFiled: April 1, 2011Date of Patent: May 22, 2012Assignee: Texas Instruments IncorporatedInventors: Ajay Kumar, Krishnaswamy Nagaraj
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Publication number: 20120119696Abstract: Methods and devices for detecting USB devices attached to a USB charging port are disclosed. The USB charging port includes a USB port having a first data line D+, a second data line D?, and a power line. A method includes attaching the USB device to the USB port; applying power to the USB device by way of the power line; applying a first voltage to the line D+ at the USB port by way of a first impedance; applying a second voltage to the line D? at the USB port by way of a second impedance. The voltages on the line D+ and the line D? are then monitored at the USB port. If the voltage on the line D+ is approximately equal to a first predetermined value for a predetermined period and the voltage on the line D? is below a second predetermined value, then the USB device is determined to be of an alpha type device.Type: ApplicationFiled: November 16, 2011Publication date: May 17, 2012Applicant: Texas Instruments IncorporatedInventor: Jean Picard
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Publication number: 20120121051Abstract: A novel receive timing manager is presented. The preferred embodiment of the present invention comprises an edge detection logic to detect the data transition points, a plurality of data flip-flops for storing data at different sample points, and a multiplexer to select the ideal sample point based on the transition points found. A sample window is made with multiple samples. The sample window size can be designed smaller or greater than the system clock period based on the data transfer speed and accuracy requirement.Type: ApplicationFiled: January 25, 2012Publication date: May 17, 2012Applicant: Texas Instruments IncorporatedInventors: Denis Roland Beaudoin, Ritesh Dhirajlal Sojitra, Gregory Lee Christison
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Publication number: 20120121165Abstract: A method and apparatus for Time Of Flight sensor 2-dimensional and 3-dimensional map generation. The method includes retrieving Time Of Flight sensor fixed point data to obtain four phases of Time Of Flight fixed point raw data, computing Gray scale image array and phase differential signal arrays utilizing four phases of TOF fixed point raw data, computing Gray image array and Amplitude image array for fixed point, converting the phase differential signal array from fixed point to floating point, performing the floating point division for computing Arctan, TOF depthmap, and 3-dimensional point cloud map for Q format fixed point, and generating depthmap, 3-dimensional cloud coefficients and 3-dimensional point cloud for Q format fixed point.Type: ApplicationFiled: November 11, 2011Publication date: May 17, 2012Applicant: Texas Instruments IncorporatedInventors: Dong-Ik Ko, Nara Won, Debasish Nag
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Publication number: 20120119802Abstract: A delay locked loop (DLL) with delay programmability includes a pair of delay blocks, each containing multiple delay elements, but configurable to connect a desired subset of the delay elements between input and output nodes of the respective delay blocks. The subsets of the delay elements in the two delay blocks are connected in series. The ratio of the number of delay elements programmed to form each of the two subsets determines a delay provided as an output by the DLL. In operation, a phase discriminator and a loop filter in combination with the programmed subsets in the delay blocks, operate to generate an analog error signal to compensate for process, temperature and voltage (PTV) variations in the delay provided as an output by the DLL.Type: ApplicationFiled: November 15, 2010Publication date: May 17, 2012Applicant: Texas Instruments IncorporatedInventor: Nagalinga Swamy Basayya Aremallapur
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Publication number: 20120121166Abstract: A method and apparatus for parallel object segmentation. The method includes retrieving at least a portion of a 3-dimensional point cloud data x, y, z of a frame, dividing the frame into sub-image frames if the sub-frame based object segmentation is enabled, performing fast parallel object segmentation and object segmentation verification; and performing the 3-dimensional segmentation.Type: ApplicationFiled: November 14, 2011Publication date: May 17, 2012Applicant: Texas Instruments IncorporatedInventors: Dong-Ik Ko, Victor Cheng
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Patent number: 8179810Abstract: Embodiments of the present disclosure provide a transmitter, a receiver and methods of operating a transmitter and a receiver. In one embodiment, the transmitter is for use with a base station in a in a cellular communication system and includes a scheduling unit configured to provide a primary synchronization signal selected from a group of multiple sequences, wherein at least two of the sequences have complex conjugate symmetry in the time domain. The transmitter also includes a transmit unit configured to transmit the primary synchronization signal. Additionally, the receiver includes a receive unit configured to receive a primary synchronization signal. The receiver also includes a detection unit configured to identify one of a plurality of primary synchronization signals corresponding to a communication cell location of the receiver, wherein at least two of a group of multiple sequences have complex conjugate symmetry in the time domain.Type: GrantFiled: April 30, 2008Date of Patent: May 15, 2012Assignee: Texas Instruments IncorporatedInventors: Eko N. Onggosanusi, Anand G. Dabak
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Patent number: 8179775Abstract: An electronic device includes a first circuit (111) operable to generate a precoding matrix index (PMI) vector associated with a plurality of configured subbands, and further operable to form a compressed PMI vector from the PMI vector wherein the compressed PMI vector includes one reference PMI and at least one differential subband PMI defined relative to the reference PMI; and a second circuit (113) operable to initiate transmission of a signal communicating the compressed PMI vector. Other electronic devices, processes and systems are also disclosed.Type: GrantFiled: August 8, 2008Date of Patent: May 15, 2012Assignee: Texas Instruments IncorporatedInventors: Runhua Chen, Eko N. Onggosanusi
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Patent number: 8179160Abstract: An integrated circuit (IC) includes an input/output (I/O) circuit supporting high-speed operation and multiple I/O logic-level swings. The I/O circuit includes a first output signal chain to generate outputs with a first logic level swing, and a second output signal chain to generate outputs with a second logic level swing. The outputs of the first output signal chain and the second output signal chain are connected to a same output pad of the IC. Transistors in the first output signal chain and the second output signal chain are fabricated using corresponding gate oxide characteristics. The second output signal chain includes protection circuitry to prevent transistors in the second output signal chain from being subjected to voltage stresses beyond a safe limit. An input circuit in the I/O circuit similarly includes multiple input signal chains to enable reception of input signals of different logic-level swings from a same input pad.Type: GrantFiled: December 17, 2010Date of Patent: May 15, 2012Assignee: Texas Instruments IncorporatedInventors: Rajat Chauhan, Ankur Gupta, Vikas Narang
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Patent number: 8178976Abstract: A semiconductor device includes an integrated circuit (IC) die including a substrate, and at least one through substrate via (TSV) that extends through the substrate to a protruding integral tip that includes sidewalls and a distal end. The protruding integral tip has a tip height between 1 and 50 ?m. A metal layer is on the bottom surface of the IC die, and the sidewalls and the distal end of the protruding integral tips. A semiconductor device can include an IC die that includes TSVs and a package substrate such as a lead-frame, where the IC die includes a metal layer and an electrically conductive die attach adhesive layer, such as a solder filled polymer wherein the solder is arranged in an electrically interconnected network, between the metal layer and the die pad of the lead-frame.Type: GrantFiled: May 8, 2009Date of Patent: May 15, 2012Assignee: Texas Instruments IncorporatedInventors: Rajiv Dunne, Gary P. Morrison, Satyendra S. Chauhan, Masood Murtuza, Thomas D. Bonifield
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Patent number: 8179446Abstract: A method of processing a digital video sequence is provided that includes estimating compensated motion parameters and compensated distortion parameters (compensated M/D parameters) of a compensated motion/distortion (M/D) affine transformation for a block of pixels in the digital video sequence, and applying the compensated M/D affine transformation to the block of pixels using the estimated compensated M/D parameters to generate an output block of pixels, wherein translational and rotational jitter in the block of pixels is stabilized in the output block of pixels and distortion due to skew, horizontal scaling, vertical scaling, and wobble in the block of pixels is reduced in the output block of pixels.Type: GrantFiled: March 3, 2010Date of Patent: May 15, 2012Assignee: Texas Instruments IncorporatedInventors: Wei Hong, Dennis Wei, Aziz Umit Batur
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Patent number: 8178915Abstract: An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes n-type and p-type doped portions serving as gate electrodes of n-channel and p-channel MOS transistors, respectively; a plate of a metal-to-poly storage capacitor; and a plate of poly-to-active tunneling capacitors. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad. An opening at the surface of the analog floating-gate electrode, at the location at which n-type and p-type doped portions of the floating gate electrode abut, allow formation of silicide at that location, shorting the p-n junction.Type: GrantFiled: March 23, 2011Date of Patent: May 15, 2012Assignee: Texas Instruments IncorporatedInventors: Allan T. Mitchell, Imran Mahmood Khan, Michael A. Wu
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Patent number: 8181067Abstract: An interface unit is provided in a JTAG test and debug procedure involving a plurality of processor cores. The interface unit includes a TAP unit. A switch unit is coupled to the interface unit and switch units are coupled to each of the plurality of processor/cores. When the processor/cores have advanced power management systems, a sleep inhibit signal can be applied to the processor/core state machine preventing the state machine from entering a lower power state. The parameters of the processor/core can be tested to determine when the test and debug procedures can be implemented. When the (power) parameters are to low to permit test and debug, the test and debug unit can provide a command forcing the state machine into a state for which test and debug procedures can be implemented.Type: GrantFiled: January 20, 2009Date of Patent: May 15, 2012Assignee: Texas Instruments IncorporatedInventor: Robert A. McGowan
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Patent number: 8179715Abstract: An integrated circuit containing SRAM cells with auxiliary load transistors on each data node. The integrated circuit also contains circuitry so that auxiliary load transistors in addressed SRAM cells may be biased independently of half-addressed cells. A process of operating an integrated circuit containing SRAM cells with auxiliary load transistors on each data node. The process includes biasing the auxiliary load transistors in addressed SRAM cells independently of half-addressed cells.Type: GrantFiled: May 19, 2010Date of Patent: May 15, 2012Assignee: Texas Instruments IncorporatedInventor: Theodore W. Houston
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Patent number: 8179235Abstract: A tactile input to a system having a speaker located in an enclosure with an audio port can be detected by generating a sound wave in response to a signal and sensing the phase relationship between the current phase and the voltage phase of the signal. While the audio port is open a baseline current and voltage phase difference is established. When the audio port is obstructed by a finger touch, the current and voltage phase difference is altered in response to the obstruction. While the altered phase difference is detected, a tactile event is indicated.Type: GrantFiled: June 17, 2009Date of Patent: May 15, 2012Assignee: Texas Instruments IncorporatedInventor: Laurent Le-Faucheur
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Patent number: 8179812Abstract: A digital communications system for delivering data blocks includes at least one transmit/receive unit (TRU). The TRU includes a storage element for receiving transmit data packets and retransmit data packets from a sending unit and a processing element communicatively coupled to the storage element. The processing element is configured for recognizing a failure to receive at least one other transmit data packet (missing data packet) from the sending unit, and for configuring a status control packet for transmission to the sending unit, the control packet includes a header including a next packet identifier for a next data packet anticipated to be received and a status payload portion including a missing packet identifier including the transmit packet identifier for the missing data packet. In the system, the retransmit data packet includes at least a segment of the data payload in the missing data packet associated with the missing packet identifier.Type: GrantFiled: September 23, 2008Date of Patent: May 15, 2012Assignee: Texas Instruments IncorporatedInventors: Ramanuja Vedantham, Shantanu Kangude
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Patent number: 8180635Abstract: A method for adapting acoustic models used for automatic speech recognition is provided. The method includes estimating noise in a portion of a speech signal, determining a first estimated variance scaling vector using an estimated 2-order polynomial and the noise estimation. The estimated 2-order polynomial represents a prior knowledge of a dependency of a variance scaling vector on noise, determining a second estimated variance scaling vector using statistics from prior portions of the speech signal, determining a variance scaling factor using the first estimated variance scaling vector and the second estimated variance scaling vector, and using the variance scaling factor to adapt an acoustic model.Type: GrantFiled: December 31, 2008Date of Patent: May 15, 2012Assignee: Texas Instruments IncorporatedInventors: Xiaodong Cui, Kaisheng Yao
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Patent number: 8179198Abstract: A variable gain amplifier may include a master amplifier that may be configured to generate a first current and a diode coupled with the master amplifier so that the first current passes through the diode which, when the first current is passing through the diode, generates a diode voltage signal. According to embodiments, an error amplifier may include a first input configured to receive a gain control voltage signal and a second input configured to receive the diode voltage signal. The output of the error amplifier may provide a feedback signal. The amplifier may include a circuit configured to generate at least one voltage control signal based on the feedback signal and a slave amplifier configured to adjust a gain amount based on the at least one voltage control signal.Type: GrantFiled: July 21, 2010Date of Patent: May 15, 2012Assignee: Texas Instruments IncorporatedInventors: Abhijit Kumar Das, Michel Frechette