Abstract: In one example, an amplifier for providing stable output quiescent current comprising includes a number of supply rails, an output device configured for providing an output voltage, the output device coupled to the plurality of supply rails, and an output quiescent current controller coupled to the plurality of supply rails and the output device, the output quiescent current controller to regulate the voltage in the output device to provide a consistent quiescent current in the output device.
Abstract: The video encoding rate control with the quantization parameter for basic units of macroblocks of a picture adapting to deviation from the average quantization parameter over pictures of the same type (i.e., I-pictures, P-pictures, and B-pictures).
Abstract: A dual port SRAM cell includes an auxiliary driver transistor on each data node. The SRAM cell is capable of single sided write to each data node. The auxiliary driver transistors in addressed cells may be biased independently of half-addressed cells. During write and read operations, the auxiliary driver transistors may be floated or biased. Auxiliary driver transistors in half-addressed SRAM cells may be biased. During standby modes, the auxiliary driver transistors may be floated. During sleep modes, the auxiliary driver transistors may be biased at reduced voltages. The auxiliary driver transistors in each cell may be independent or may have a common source node within each cell. Additional single sided write ports and read buffers may be added. A process of operating an integrated circuit that includes performing a single-sided write bit-side low, a single-sided write bit-side high, and a read bit-side operation.
Abstract: A method of operating a phase locked loop (FIG. 5) for a wireless receiver is disclosed. The method includes receiving a reference signal (503) having a first and a second plurality of cycles and receiving a feedback signal (512) having the first and the second plurality of cycles. The feedback signal is compared (504) to the reference signal. A plurality of phase errors is produced for each cycle of (UP, FIG. 10A) the first plurality of cycles in response to the step of comparing.
Abstract: A fractional divider has been provided that allows for division ratios of 1:1 to 1:2N-1 with fine fractional resolution. To accomplish this, a phase blender (which is under the control of a state machine) is used to “blend” or interpolate consecutive phases of a clock signal from a delay locked loop to achieve a low deterministic jitter, while a sigma delta modulator can also be used to maintain low deterministic jitter while achieving the desired frequency resolution.
Abstract: In conventional pipelined analog-to-digital converters (ADCs), it is common to employ digital-to-analog converters (DACs) in the ADC stages that use two-state switches or segments. A problem with this arrangement is that for each DAC state there is a noise contribution from each DAC switch, resulting from its current source. Here, however, a DAC is employed that uses three-state DAC switches, which reduces the noise contributions from the DAC switches' current sources and reduces the amount of area used.
Abstract: A Sigma-Delta Modulator (SDM) has a summing junction that receives an input signal and a feedback signal, a multi-level analog-to-digital converter (ADC) that receives the SDM input signal and generates an ADC output, a first analog switch that receives the ADC output and generates a plurality of reference voltages, a second analog switch generating the feedback signal, where the feedback signal is selected from one of the reference voltages.
Abstract: An LDO regulator (10) produces an output voltage (Vout) by applying the output voltage to a feedback input (6) of a differential input stage (10A) and applying an output (3) of the differential input stage to a gate of a first follower transistor (MP4) having a source coupled to an input (8) of a class AB output stage (10C) which generates the output voltage. Demanded load current is supplied by the output voltage during a dip in its value to a gate of a second follower transistor (MP5) having a gate coupled to the output of the input stage to decrease current in a current mirror (MN5,6) having an output coupled to a current source (I1) and a gate of an amplifying transistor (MN7). This causes the current source to rapidly turn on the amplifying transistor to cause it to rapidly turn on a cascode transistor (MN3), causing it to turn on a pass transistor (MP3) of the output stage.
Abstract: In a first embodiment a TAP of IEEE standard 1149.1 is allowed to commandeer control from a WSP of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is rendered controllable by the TAP. In a second embodiment (1) the TAP and WSP based architectures are merged together such that the sharing of the previously described architectural elements are possible, and (2) the TAP and WSP test interfaces are merged into a single optimized test interface that is operable to perform all operations of each separate test interface. One approach provides for the TAP to maintain access and control of the TAP instruction register, but provides for a selected data register to be accessed and controlled by either the TAP+ATC or by the discrete CaptureDR, UpdateDR, TransferDR, ShiftDR, and ClockDR WSP data register control signals.
Abstract: A method of video encoding is provided that includes computing spatial variance for video data in a block of a video sequence, estimating a first bit-rate based on the spatial variance, a transform coefficient threshold, and variance multiplicative factors empirically determined for first transform coefficients, and encoding the block based on the first bit-rate.
Abstract: With Successive Approximation Register (SAR) analog-to-digital converters (ADCs), there are several different architectures. One of these architectures is a “convert and shut down” architecture, where an internal amplifier is powered down during the sampling phase to reduce power consumption. This powering down comes at a price in that a portion of the convert phase is lost waiting for the amplifier to be powered back up. Here, an apparatus is provided that makes use of the entire convert phase by coarsely resolving a few bits during the period in which the amplifier is powering up to have an increased resolution over conventional SAR ADCs with “convert and shut down” architecture, while maintaining low power consumption.
Abstract: A leadframe for the assembly of a semiconductor chip has regions (112) with an original smooth surface of glossy appearance and regions (113, 114, 210) of a frosty appearance with rough surface contours. The regions of rough surface contours include two-dimensional arrays of spots (401) comprising a central area (402) below the original surface (400) and a piled ring (403) above the original surface. The piled ring (403) consists of the leadframe material in amorphous configuration.
Abstract: A method and system for testing a semiconductor package. At least some of the illustrative embodiments are methods comprising testing a semiconductor package unit (150, 420) by electrically coupling a top printed circuit board (208, 420) to a top-side of a semiconductor package unit (150, 420), the coupling using electrically conductive top-side pogo pins (201A, 420), and a pair of adjacent top-side pogo pins (201A, 420) bridged using an electrically conductive path (302, 420), electrically coupling a bottom printed circuit board (210, 430) to a bottom-side of the semiconductor package unit (150, 430), the coupling using electrically conductive bottom-side pogo pins (201B, 430), said top-side pogo pins (201A, 430) and said bottom-side pogo pins are of substantially equal height (201B, 430), and transmitting test signals from the bottom printed circuit board to the semiconductor device package by way of the bottom-side pogo pins (210, 440).
Abstract: A receiver with selective sign inversion which can compensate for cross-over conversion is described. Some inputs may be a differential data inputs; a sign select input; a converter having inputs coupled to the differential data inputs and having first and second outputs, wherein the converter is adapted to convert a differential data signal received at the differential data input into a digital data output at the first output and a sign signal at the second output; and a selective sign inverter having a first input coupled to the sign output of the analogue-to-digital converter, a second input coupled to the sign select input and an output, wherein the signal received at the first input of the selective sign inverter is selectively inverted in dependence on the signal received at the second input in order to provide the modified sign select signal.
Abstract: A layered code-excited linear prediction (CELP) encoder, an Adaptive Multirate Wideband (AMR-WB) encoder and methods of CELP encoding and decoding. In one embodiment, the encoder includes: (1) a core layer subencoder and (2) at least one enhancement layer subencoder, at least one of the core layer subencoder and the enhancement layer subencoder having first and second adaptive codebooks and configured to retrieve a pitch lag estimate from the second adaptive codebook and perform a closed-loop search of the first adaptive codebook based on the pitch lag estimate.
Abstract: Method, video encoders, and digital systems are provide in which motion vector determination includes selecting a plurality of candidate motion vectors for a macroblock using a cost function including both a block distortion measure and a motion vector cost measure for single-partition motion vectors in the plurality of candidate motion vectors and using a cost function including a distortion measure without a motion vector cost measure for multi-partition motion vectors in the plurality of candidate motion vectors, and refining the plurality of candidate motion vectors to obtain a refined plurality of candidate motion vectors, wherein multi-partition motion vectors of the plurality of candidate motion vectors are refined using a cost function including a distortion measure without a motion vector cost measure and single-partition motion vectors of the plurality of candidate motion vectors are refined using a cost function including both a block distortion measure and a motion vector cost measure.
Abstract: An SRAM cell containing an auxiliary driver transistor is configured for a single sided write operation. The auxiliary driver transistor may be added to a 5-transistor single-sided-write SRAM cell or to a 7-transistor single-sided-write SRAM cell. The SRAM cell may also include a read buffer. During read operations, the auxiliary drivers are biased. During write operations, the auxiliary drivers in half-addressed SRAM cells are biased and the auxiliary drivers in the addressed SRAM cells may be floated or biased.
Abstract: A system and method for using an optical lightguide in a projection display system. A plurality of light sources provides a plurality of colored light to a lightguide. The lightguide may include alternating layers of a relatively high refractive index material and a relatively low refractive index material. In an embodiment, the layers of the lightguide are tapered. In another embodiment, the lightguide includes a light pipe having a lenticular array on the entrance face of the light pipe. Optionally, the light pipe may be tapered. The lightguide provides a line of light to a scanning element, which in turn redirects the light to a spatial light modulator.
Type:
Grant
Filed:
March 31, 2008
Date of Patent:
April 17, 2012
Assignee:
Texas Instruments Incorporated
Inventors:
Terry Alan Bartlett, Patrick Rene Destain
Abstract: A method of generating a spread spectrum clock signal for a line imaging device including receiving a line length value of the line imaging device, receiving a first clock signal indicative of a system timing signal in the line imaging device, generating a spreading waveform having a frequency as a function of the line length value and having a total number of clock cycles matching the line length value, and modulating the first clock signal using said spreading waveform to generate the spread spectrum clock signal where the spread spectrum clock signal is used for driving the imaging, data sampling and digitizing, and data transfer operation of the line imaging device. The spread spectrum clock has the same clock frequency variation for each scan line of the line imaging device.
Abstract: A timing skew estimation system is disclosed that includes a plurality of interleaved analog-to-digital converter circuits (ADCs), a timing mismatch estimation unit, and a correction unit. The timing mismatch estimation unit calculates a correlation between each of the plurality of ADCs. Then the timing mismatch estimation unit calculates a cost function for each of the plurality of ADCs, except the reference ADC. The timing mismatch estimation unit further calculates a gradient for each of the plurality of ADCs, except the reference ADC.
Type:
Grant
Filed:
August 31, 2010
Date of Patent:
April 17, 2012
Assignee:
Texas Instruments Incorporated
Inventors:
Naor Goldman, Noam Tal, Yonina Eldar, Charles Sestok, Efrat Levy