Abstract: A method for manufacturing a semiconductor device that comprises implanting a first dopant type in a well region of a substrate to form implanted sub-regions that are separated by non-implanted areas of the well region. The method also comprises forming an oxide layer over the well region, such that an oxide-converted first thickness of the implanted sub-regions is greater than an oxide-converted second thickness of the non-implanted areas. The method further comprises removing the oxide layer to form a topography feature on the well region. The topography feature comprises a surface pattern of higher and lower portions. The higher portions correspond to locations of the non-implanted areas and the lower portions correspond to the implanted sub-regions.

Abstract: This invention is a solid-state image pickup device that solves the problem of limited dynamic range in the high luminance region in an image sensor having white pixels. White pixels or yellow pixels and at least red pixels, green pixels or blue pixels are arranged in array form on the light receiving surface of a semiconductor substrate. White pixels or yellow pixels have an additional capacitance CS connected to the photodiode via the floating diffusion, a capacitance coupling transistor S that can couple or separate the floating diffusion and the additional capacitance. The proportion of white or yellow pixels to the total number of pixels is higher in a central portion of the light receiving surface than a peripheral portion. The white or yellow pixel may share a floating diffusion with a red, green or blue pixel.

Abstract: A buffer is provided. The buffer includes a first switch and a second switch coupled in series at a first output node, a third switch and a fourth switch coupled in series at a second output node, a first current source and a second current source. The first current source is coupled with one side to the first switch and the third switch and with another side to a first supply voltage, the second current source is coupled with one side to the second switch and the fourth switch and with a second side to a second supply voltage. The first current source is configured to adjust an output swing in a first operation mode and in a second operation. The second current source is configured to adjust a common mode voltage level of the output signal in the first operation mode and to provide maximum series resistance in the second operation mode.

Abstract: A process of selecting alternative test circuitry within an integrated circuit enables a test access port. Scan test instruction data is loaded into an instruction register of a test access port TAP, the instruction data including information for selecting the alternative test circuitry. An Update-IR instruction update operation is performed at the end of the loading to output scan test control signals from the instruction register. A lockout signal is changed to an active state to disable the test access port and enable scan test circuits.

Abstract: The invention relates to an electronic device that includes a plurality of buffers and a phase locked loop. For each buffer a fractional divider is provided which is coupled to receive the output from the phase locked loop and configured to feed a divided output signal to a respective buffer. A spread spectrum clock control logic stage in the spread spectrum clock (SSC) is provided which is configured to individually adjust a value of the division of each fractional divider in order to individually and independently modulate the output signal of each fractional divider according to a spread spectrum modulation scheme.

Abstract: Performance of wireless charging systems may be significantly degraded when parasitic metal objects come in close proximity to the transmitting coil. Some of the transmitted energy may be coupled by these metal objects and wasted as heat. This may create a danger as the metal objects may get hot enough to create a fire hazard, to cause plastic parts deformation, or operator skin burns when touched. Systems and methods of wireless power transfer system with interference detection disclosed herein detects possible excessive energy transfer associated with parasitic metal objects placed in close proximity with system coils by comparing power received on the receiving side of the system with the power consumed on the primary side considering known losses in the system. If the result of such comparison shows that power consumed on the primary side substantially exceeds power received on the secondary side, the system may terminate operation.

Abstract: An electronic assembly includes an IC die including a semiconductor top surface having active circuitry thereon and a bottom surface, and at least one protruding bonding feature having sidewall surfaces and a leading edge surface extending outward from the IC die. A workpiece has a workpiece surface including at least one electrical connector and at least one framed hollow receptacle coupled to the electrical connector. The receptacle is formed from metal and includes sidewall portions and a bent top that defines a cavity. The bent top includes bent peripheral shelf regions that point downward into the cavity and towards the sidewall portions. The protruding bonding feature is inserted within the cavity of the receptacle and contacts the bent peripheral shelf regions along a contact area to form a metallic joint, wherein the contact area is at least primarily along the sidewall surfaces.

Abstract: Recently, there has been an increased desire to measure load currents of class-D amplifiers to improve performance. The traditional solution has been to include one or more discrete components in series with the load, but this degrades performance. Here, however, circuit is provided (which includes sample-and-hold circuit) that accurately measures load currents without inhibiting performance and that is not inhibited by the phase differences between the load voltage and load current.

Abstract: A wireless communication system. The system comprises transmitter circuitry (BST1), the transmitter circuitry comprising encoder circuitry (50) for transmitting a plurality of frames (FR). Each of the plurality of frames comprises a primary synchronization code (PCS) and a secondary synchronization code (SSC). The encoder circuitry comprises of circuitry (501) for providing the primary synchronization code in response to a first sequence (32). The encoder circuitry further comprises circuitry (502) for providing the secondary synchronization code in response to a second sequence (54) and a third sequence (56). The second sequence is selected from a plurality of sequences. Each of the plurality of sequences is orthogonal with respect to all other sequences in the plurality of sequences. The third sequence comprises a subset of bits from the first sequence.

Abstract: According to one embodiment of the present invention, a system for encoding an optical spectrum includes a dispersive element, a digital micromirror device (DMD) array, a detector, and a controller. The dispersive element receives light from a source and disperses the light to yield light components of different wavelengths. The digital micromirror device (DMD) array has micromirrors that modulate the light to encode an optical spectrum of the light. The detector detects the light that has been modulated. The controller generates an intensity versus time waveform representing the optical spectrum of the detected light.

Abstract: This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations. In a fifth aspect of the present disclosure, an interface select circuit, FIGS. 41-49, provides for selectively using either the 5 signal interface of FIG. 41 or the 3 signal interface of FIG. 8.

Abstract: A signal converting system is described that has a multi-segment digital to analog converter coupled to one or more error shaping loops. Each error shaping loop includes a quantizer with a feedback loop configured to generate a control signal responsive to a stream of symbols and to an error signal. Each error shaping loop also includes an inter-symbol-interference (ISI) shaping loop coupled to receive the control signal and to produce an ISI portion of the error signal that is responsive to inter-symbol transition rate.

Abstract: Oscillator circuit for radio frequency transceivers. An oscillator circuit includes a first oscillator that generates a signal having a first frequency and a second oscillator that generates a signal having a second frequency. The oscillator circuit includes a mixer that is responsive to the signal having the first frequency and the signal having the second frequency to provide a signal having a third frequency and one or more frequency components. The oscillator circuit includes a filter that is responsive to the signal from the mixer to attenuate the one or more frequency components and provide a signal having a desired frequency. The oscillator circuit includes a correction circuit to correct a drift in at least one of the first frequency and the second frequency by controlling the second frequency, thereby correcting the drift in the third frequency and the desired frequency.

Abstract: A digital subscriber line (DSL) modem that has a canceller digital filter for cancelling crosstalk and RF interference in a received DSL signal is disclosed. The modem includes common-mode sense circuitry and also differential-mode sense circuitry. Samples of the common-mode signal are acquired during a “quiet” period of initialization of the DSL modem, and samples of the differential-mode signal are acquired during live transmission of a DSL signal. An estimate of an autocorrelation function is obtained from the common-mode samples, and a cross-correlation of the common-mode samples and differential-mode samples is also estimated. Digital filter coefficients are derived from these estimates, based on the assumption that the common-mode samples acquired during the “quiet” phase represent crosstalk and RF interference present during differential-mode communications.

Abstract: A Smart Card module with flip-assembled chip (101) on a metallic strap (112) adhering to an insulating substrate (111). Chip (101) is in the gap (122) of a metal carrier (120), strap (112) conductively attached to the carrier. Carrier (120) is designed to practically surround the chip, and has a thickness about equal to the chip thickness. Overall module thickness is less than 250 ?m without dangerously thinning the chip. Additional strength may be acquired by filling any space of gap (122) not occupied by chip (101) with encapsulation compound (150). Metal carrier (120) further provides contact areas (120a, 120b) for higher level system interconnection (stacking of modules).

Abstract: A compensatory memory system is described. This memory system substantially improves performance by adapting an associated delay in a way that optimizes circuit performance.

Abstract: A method for generating and evaluating a table model for circuit simulation in N dimensions employing mathematical expressions for modeling a device. The table model uses an unstructured N-dimensional grid for approximating the expressions.

Abstract: An output stage for an LED driver is provided. In particular, a low voltage clamp, which uses several cascode circuits, is provided to protect low voltage switching transistors in the range of two times higher voltage application under both normal and fault conditions. Additionally, a circuit for regulating the bias voltage applied to each of the cascode circuits is provided to prevent damage during startup, while an internal voltage regulator is settling.

Abstract: In some developing interconnect technologies, such as chip-to-chip optical interconnect or metal waveguide interconnects, misalignment can be a serious issue. Here, however, a interconnect that uses an on-chip directional antenna (which operates in the sub-millimeter range) to form a radio frequency (RF) interconnect through a dielectric waveguide is provided. This system allows for misalignment while providing the increased communication bandwidth.

Abstract: Transmission lines employing transmission line units or elements within integrated circuits (ICs) are well-known. Typically, different heights for these transmission line units can vary the characteristics of the cell (and transmission line), and there is typically a tradeoff between impedance and space (layout) specifications. Here, a transmission line is provided, which is generally comprised of elements of the same general width, but having differing or tapered heights that allow for impedance adjustments for high frequency applications (i.e., 160 GHz). For example, a transmission line that is coupled to a balun, with the transmission line units decreasing in height near the balun's center tap to adjust the impedance of the transmission line for the balun, is shown.