Abstract: Providing interpolated signals with enhanced signal-to-noise-ratio (SNR). In an embodiment, for each digital sample (of an analog signal) having strength Dn, N values are inserted, with the kth inserted value having a strength of Dn(1±Dk), wherein Dk is selected randomly from within a range set according to quantization noise. The received digital samples along with inserted digital values are provided as the interpolated signal corresponding to the input signal represented by the received digital samples.

Abstract: A method evaluating threshold of a data cell in a memory device including a programming locus coupled with the data cell for receiving a programming signal setting a stored signal level in the data cell and responding to a read signal to indicate the stored signal at a read locus; includes the steps of: (a) in no particular order: (1) selecting a test threshold signal; and (2) setting a read signal at a non-read level; (b) applying the test threshold signal to the programming locus; (c) cycling the read signal between a read level and a non-read level while applying the test threshold signal to the programming locus to present at least two test signals at the read locus when the read signal is at the read level; and (d) while cycling, observing whether the at least two test signals manifest a difference greater than a predetermined amount.

Abstract: The disclosed embodiments reveal an analog MEMS device with a pivotal micromirror that is supported by one or more beams that provide non-linear resistance. An electrode can electrostatically attract the micromirror, while the beam(s) provide resistance to deflection. When the forces equalize, the micromirror is held at a target angle. The beam support disclosed in the embodiments is superior to conventional torsion hinge supports, because it provides non-linear support for the micromirror, better matching the non-linear nature of the electrostatic force.

Abstract: A method for manufacturing a semiconductor device that comprises forming an oxide layer over a substrate. A polysilicon layer is disposed outwardly from the oxide layer, wherein the polysilicon layer forms a floating gate. A PSG layer is disposed outwardly from the polysilicon layer and planarized. The device is pattern etched to form a capacitor channel, wherein the capacitor channel is disposed substantially above the floating gate formed from the polysilicon layer. A dielectric layer is formed in the capacitor channel disposed outwardly from the polysilicon layer. A tungsten plug operable to substantially fill the capacitor channel is formed.

Abstract: A reduced search space minimum distance decoding method provides average probability of error performance close to optimal MAP decoding. The decoding algorithm provides dramatic complexity reductions compared with MAP decoding. A a sub-optimal decoder receives a collection of signal vectors y1 . . . yk, with k denoting a positive integer and generates an estimated transmitted multidimensional symbol {tilde over (S)}. The estimated transmitted multidimensional symbol {tilde over (S)} is decoded using hierarchical subset decoding a subset is determined therefrom. A reduced search space V is generated and minimum distance decoding is used to decode the received symbol vectors y1 . . . yk in the reduced search space V. one or more of the following: an estimated multidimensional symbol {tilde over (S)}, soft bit information, or hard bit information are cienerated therefrom.

Abstract: The teachings of the present invention provide a method for modeling an integrated circuit system including a microchip, an integrated circuit package, and a printed circuit board. The method includes generating a configuration file including parasitics regarding ball grid arrays and vias intended for use in design of the integrated circuit system. A netlist may be generated using the configuration file. In accordance with a particular embodiment of the present invention, the operation of the integrated circuit system may be simulated to determine anticipated operating characteristics of the integrated circuit system.

Abstract: An amplifier system in accordance with an aspect of the present invention comprises a switching amplifier that drives a load with a pulse-width modulated (PWM) output signal that varies between first and second rails based on a first control input signal, and a common mode supply that provides a switching signal that varies between third and fourth rails to maintain a common mode voltage of the load at a level that is between the first and second rails.

Abstract: Apparatus for converting orthogonal data to a format suitable for displaying the image on a diamond-shaped pixel array. A stream of digital data formatted for being displayed on an orthogonal pixel array is received at an IIR (Infinite Impulse Response) filter. The digital data stream is conditioned so that it can be sub-sampled and used on a diamond-shaped pixel array with minimal distortion. The sub-sampling comprises dropping even pixels in odd numbered orthogonal rows and dropping odd pixels on all even numbered rows. A tap is included at the IIR filter for providing a partially filtered version of the data stream to circuitry for reducing “ringing” of the image. The circuitry also detects edges in the image and emphasizes vertical transitions when a vertical edge is detected and emphasizes horizontal transitions when a vertical edge is not detected.

Abstract: A data processing apparatus simultaneously sorts n input data words into a sorted list of m list entries. The apparatus includes a pre-sorting network sorting the n input data words and a sorting network storing up to m list entries and storing respective input data words into the m list entries. The pre-sorting network includes a set of comparators for each unique pair of input data words, and a set of n multiplexers outputting a selected one of the n input data words, and a decoder circuit controlling the multiplexers responsive to the comparisons. The sorting network includes m basic units storing current list entries ordered from greatest to least. Each cycle the basic units selecting for storage the current list entry, a current list entry of a basic units storing greater list entries or one of the input data words.

Abstract: The fully differential large swing variable gain amplifier circuit includes: a first 5-transistor transconductor having a common mode node; and a second 5-transistor transconductor having a common mode node coupled to the common mode node of the first 5-transistor transconductor, wherein the second 5-transistor transconductor operates 180 degrees out of phase with the first 5-transistor transconductor.

Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that tailor applied strain profiles to channel regions of transistor devices. A strain profile is selected for the channel regions (104). Recessed regions are formed (106) in active regions of a semiconductor device after formation of gate structures according to the selected strain profile. A recess etch (106) is employed to remove a surface portion of the active regions thereby forming the recess regions. Subsequently, a composition controlled recess structure is formed (108) within the recessed regions according to the selected strain profile. The recess structure is comprised of a strain inducing material, wherein one or more of its components are controlled and/or adjusted during formation (108) to tailor the applied vertical channel strain profile.

Abstract: Methods and systems are disclosed for preprocessing video display pixel data. A preprocessor is provided with a selectable gamma correction mode and a selectable palette lookup mode. In palette lookup mode, a LUT memory area is used for performing a palette lookup for each of the red, green, and blue components of video pixel data, concatenating the paletted red, green, and blue components, and outputting paletted preprocessed pixel data. In gamma correction mode, the preprocessor uses the same LUT memory area for performing gamma correction on each of the red, green, and blue components of video pixel data, concatenating the gamma-corrected red, green, and blue components, and outputting a gamma-corrected preprocessed pixel data.

Abstract: A semiconductor device including a vertical assembly of semiconductor chips interconnected on a substrate with one or more metal standoffs providing a fixed space between each supporting chip and a next successive vertically stacked chip is described. The device is fabricated by patterning islands of aluminum atop the passivation layer of each supporting chip simultaneously with processing to form bond pad caps. The fabrication process requires no additional cost, and has the advantage of providing standoffs for a plurality of chips by processing in wafer form, thereby avoiding additional assembly costs. Further, the standoffs provide improved thermal dissipation for the device and a uniform, stable bonding surface for wire bonding each of the chips to the substrate.

Abstract: An electrostatic discharge (ESD) device for protecting a power amplifier circuit is disclosed. The ESD device comprises a first ESD protection circuit coupled between a positive terminal of a supply voltage and a negative terminal of the supply voltage, and a second ESD protection circuit coupled between the negative terminal of the supply voltage and an output terminal of the power amplifier circuit, wherein a first current path is formed from the positive terminal to the output terminal through the first and second ESD protection circuits. A circuit device operative to increase impedance of a second current path from the positive terminal to the output terminal through the power amplifier circuit to divert current from the second current path to the first current path in the course of an ESD event.

Abstract: This invention provide parallel interference cancellation for wireless communication base stations. Received user inputs symbols are spread by means of pseudo-noise sequences to form user input chip vectors. These are added together and interpreted to form chip vectors of interference samples. These chip vectores are despread to form interference output symbols by pseudo-noise sequences. The interference output signals are subtracted from the received user input symbols to obtain a first estimate of transmitted symbols. This process may be continued for two or more iterations to obtain better interference cancellation.

Abstract: Scan testing of plural target electrical circuits, such as circuits 1 through N, becomes accelerated by using the scan test response data output from one circuit, such as circuit 1, as the scan test stimulus data for another circuit, such as circuit 2. After reset, a scan path captures the output response data from the reset stimulus from all circuits. A tester then shifts the captured data only the length of the first circuit's scan path while loading the first circuit's scan path with new test stimulus data. The new response data from all the circuits then is captured in the scan path. This shift and capture cycle is repeated until the first circuit is tested. The first circuit is then disabled and any remaining stimulus data is applied to the second circuit. This process is repeated until all the circuits are tested. A data retaining boundary scan cell used in the scan testing connects the output of an additional multiplexer as the input to a boundary cell.

Abstract: A method of performing a pattern fill operation of a pattern into a clipping region divides dividing the pattern into a plurality of bands. For each band the method renders the band as a bit map into a band cache. For each tiling of the pattern into the clipping region the method clips the bit map of a current band to the clipping region and copies the clipped bit map into a corresponding location of a page bit map. The plurality of bands of the pattern are preferable aligned with scan lines of the printed page. The bands may correspond to individual scan lines. The method select the number of bands so that each band may be stored within a predetermined amount of band cache memory.

Abstract: A method (200) of forming an isolation structure is presented, in which a hard mask layer (304, 308) is formed (204, 206) over the isolation and active regions (305, 303) of a semiconductor body (306), and a dopant is selectively provided to a portion of the active region (303) proximate the isolation region (305) to create a threshold voltage compensation region (318). After the compensation region (318) is created, the hard mask layer (304, 308) is patterned (218) to create a patterned hard mask. The patterned hard mask is then used in forming (222) a trench (323) in the isolation region (305) near the compensation region (318), and the trench (323) is then filled (224) with a dielectric material (338).

Abstract: A system for, and method of, text-to-phoneme (TTP) mapping and a digital signal processor (DSP) incorporating the system or the method. In one embodiment, the system includes: (1) a letter-to-phoneme (LTP) mapping generator configured to generate an LTP mapping by iteratively aligning a full training set with a set of correctly aligned entries based on statistics of phonemes and letters from the set of correctly aligned entries and redefining the full training set as a union of the set of correctly aligned entries and a set of incorrectly aligned entries created during the aligning and (2) a model trainer configured to update prior probabilities of LTP mappings generated by the LTP generator and evaluate whether the LTP mappings are suitable for training a decision-tree-based pronunciation model (DTPM).

Abstract: A technique to pre-charge a CAM block array that includes a plurality of CAM blocks that is organized into at least one rectangular array having rows each having a plurality of CAM blocks, a group of CAM cells and associated read/write bit lines connecting the group of CAM cells to a write/search driver and one or more precharge circuits. In one example embodiment, this is accomplished by precharging each read/write bit line substantially after completing a read cycle using the one or more precharge circuits. Then, precharging each read/write bit line substantially after completing a write cycle using a write/search bit line decoder and driver circuit, followed by precharging each search bit line in the CAM block array using the write/search bit line decoder and driver circuit substantially after completing a search operation.