Abstract: Providing color management includes receiving measurements of the intensity of colors. A light source generates light beams to yield the colors, where the light beams are generated in accordance to image data to create an image. A target color value is established. A duty cycle sequence operable to control the light source is selected in accordance with the measurements and the target color value. Current levels for currents provided to the light source are selected in accordance with the duty cycle sequence and the target color value.

Abstract: According to one embodiment, a method for compensating for inadequate bit resolution in a light processing system includes receiving a plurality of values each indicative of an intensity level for a pixel to be displayed. Each of the values is represented by a plurality of bits of data. The method also includes determining a quantization step size for the plurality of bits of data. For at least one particular pixel of the pixels, a set of consecutive pixels including the particular pixel is selected. The method also includes determining a difference between the value associated with the particular pixel in the set and each value associated with the other pixels in the set, and also determining that all of the determined differences are less than or equal to the quantization step size. In response, a filtered value for the particular pixel in the set is generated based at least on some of the pixels in the set in addition to the particular pixel.

Abstract: Various systems and methods involving image data conversion are discussed herein. As one example, a method for image data conversion is disclosed. The method includes receiving an image in a particular color space, and converting the received image from the particular color space to a reduced color space. Then, a conversion is performed to convert the image from the reduced color space to the full color space.

Abstract: A multi-threaded microprocessor (1105) for processing instructions in threads. The microprocessor (1105) includes first and second decode pipelines (1730.0, 1730.1), first and second execute pipelines (1740, 1750), and coupling circuitry (1916) operable in a first mode to couple first and second threads from the first and second decode pipelines (1730.0, 1730.1) to the first and second execute pipelines (1740, 1750) respectively, and the coupling circuitry (1916) operable in a second mode to couple the first thread to both the first and second execute pipelines (1740, 1750). Various processes of manufacture, articles of manufacture, processes and methods of operation, circuits, devices, and systems are disclosed.

Abstract: A wireless handset having the capability of browsing full Internet web pages is disclosed. The handset includes a position sensing device, such as an optical sensor or a mouse ball and rollers, at its bottom surface. In an Internet browsing operating mode, a portion of a web page is displayed on a graphics display of the handset. Movement of the handset along a solid surface, similar to the movement of a computer mouse, will change the portion of the web page displayed. A cursor is displayed over the web page, and handset keys correspond to “left-click” and “right-click” functions in this mode. In a text entry mode, a portion of a keyboard layout is displayed, so that selection of characters using the cursor and movement of the handset is effected.

Abstract: A network infrastructure device includes a receiver operable to receive packets when operably connected to a communication network; and a processor cooperatively operable with the transceiver. The processor can receive a packet on an interface corresponding to the transceiver. Also, the processor can map the packet to one of several queues and to one of several classifications, based on an indication of priority of handling in a header in the packet and/or an indication of priority in a configuration of the interface. The processor also checks for congestion in the queues with respect to the classification of the packet, and checks for congestion in the one queue with respect to the one classification. The processor queues the packet if there is no congestion, otherwise the processor drops the packet.

Abstract: A directional controller for a device is provided. The directional controller consists of keypad contacts, a keyboard, and a button. The keypad contacts are on a printed circuit board. The keyboard has more than four keys and each key is disposed adjacent to one of the keypad contacts. The button is operable for pivoting engagement with the more than four keys to promote contact between the more than four keys and the adjacent one of the keypad contacts.

Abstract: Various systems and methods for common mode detection are disclosed. As one example, a common mode detection circuit including a differential input stage, a common mode replica stage, and an amplifier is disclosed. The differential input stage exhibits an input common mode, and includes two differential inputs. A signal from the differential input stage representing the input common mode is electrically coupled to an input of the amplifier. Another input of the amplifier is electrically coupled to the common mode replica stage, and the amplifier outputs a signal indicative of the input common mode.

Abstract: The present invention provides a spurious tone suppressor for use with a power supply system. In one embodiment, the spurious tone suppressor includes an error signal generator configured to provide a spur error signal proportional to a spur signal associated with the power supply system. Additionally, the spurious tone suppressor also includes an adaptive spur cancellation engine coupled to the error signal generator and configured to adaptively process the spur error signal and generate a corresponding anti-spur signal that is injected into the power supply system to suppress the spur signal.

Abstract: According to one embodiment of the invention, a silicon-on-insulator device includes an insulative layer formed overlying a substrate and a source and drain region formed overlying the insulative layer. The source region and the drain region comprise a material having a first conductivity type. A body region is disposed between the source region and the drain region and overlying the insulative layer. The body region comprises a material having a second conductivity type. A gate insulative layer overlies the body region. This device also includes a gate region overlying the gate insulative layer. The device also includes a diode circuit conductively coupled to the source region and a conductive connection coupling the gate region to the diode circuit.

Abstract: A Class-D amplifier system may include an input stage that includes an Nth order filter, where N>1. The input stage filters an input signal to provide a filtered output signal, an input of the input stage being configured to receive the input signal as a digital pulse-width-modulated (PWM) signal. A comparator provides a quantized output signal based on the filtered output signal. An output stage is connected between a first voltage rail and a second voltage rail. The output stage provides a switching output signal at an output that varies between the first voltage rail and the second voltage rail based on the quantized output signal. A feedback path connects the output of the output stage with the input of the input stage, such that the Nth order filter compensates for variations in at least one of the first voltage rail and the second voltage rail.

Abstract: The present invention provides a method for manufacturing an interconnect and a method for manufacturing an integrated circuit including the interconnect. The method of manufacturing an interconnect, among other steps, includes forming a via (160) in a substrate (130) and then forming a base getter material (210) in the via (160). The method further includes forming a photoresist layer (410) over the base getter material (210), the photoresist layer (410) having an opening (420) therein positioned over the via (160), and etching a trench (510) into the substrate (130) using the opening (420) in the photoresist layer (410).

Abstract: Correcting a mask pattern includes accessing the mask pattern segmented into segments. An attribute value is established for each segment, where the attribute value for a segment describes an attribute of the segment. The following is repeated for one or more of the attribute values to generate a corrected mask pattern: selecting segments using one or more attribute values; calculating a current correction value for each of the selected segments with respect to previously selected segments updated according to previously calculated correction values; and updating the selected segments according to the current correction values.

Abstract: A system and method for detecting a security violation using an error correction code. Some illustrative embodiments may be a method used in a computing system comprising reading a codeword comprising data and an error correction code (ECC) (the ECC associated with the data), deriving an error location polynomial (ELP) from the codeword, determining a total number of codeword errors from the ELP, and preventing access to the data within the codeword if the total number of codeword errors exceeds a maximum number of correctable errors.

Abstract: A semiconductor device (102) that includes a drain extended PMOS transistor (CT1a) is provided, as well as fabrication methods (202) therefore. In forming the PMOS transistor, a drain (124) of the transistor is formed over a region (125) of a p-type upper epitaxial layer (106), where the region (125) of the p-type upper epitaxial layer (106) is sandwiched between a left P-WELL region (130a) and a right P-WELL region (130b) formed within the p-type upper epitaxial layer (106). The p-type upper epitaxial layer (106) is formed over a semiconductor body (104) that has an n-buried layer (108) formed therein. This arrangement serves to increase the breakdown voltage (BVdss) of the drain extended PMOS transistor.

Abstract: An apparatus for mitigating condensation formation on a device interface board during low-temperature semiconductor device testing includes a nozzle. The nozzle includes an input orifice for receiving gas from a gas source and at least one output orifice for discharging gas from the nozzle against a surface of the device interface board. The area of the at least one output orifice is substantially greater than the area of input orifice.

Abstract: A method is provided for equalization of nonlinear distortion in a distorted signal comprising the steps of: digitizing the distorted signal and passing the digitized distorted signal through an inverse non-linear transfer function to equalize the nonlinear distortion. Other systems and methods are disclosed.

Abstract: The present invention provides an integrated circuit and a method of manufacture therefor. The integrated circuit (100), in one embodiment without limitation, includes a dielectric layer (120) located over a wafer substrate (110), and a semiconductor substrate (130) located over the dielectric layer (120), the semiconductor substrate (130) having one or more transistor devices (160) located therein or thereon. The integrated circuit (100) may further include an interconnect (180) extending entirely through the semiconductor substrate (130) and the dielectric layer (120), thereby electrically contacting the wafer substrate (110), and one or more isolation structures (150) extending entirely through the semiconductor substrate (130) to the dielectric layer (120).

Abstract: In order to minimize light diffraction along the direction of switching and more particularly light diffraction into the acceptance cone of the collection optics, in the present invention, micromirrors are provided which are not rectangular. Also, in order to minimize the cost of the illumination optics and the size of the display unit of the present invention, the light source is placed orthogonal to the rows (or columns) of the array, and/or the light source is placed orthogonal to a side of the frame defining the active area of the array. The incident light beam, though orthogonal to the sides of the active area, is not however, orthogonal to any substantial portion of sides of the individual micromirrors in the array. Orthogonal sides cause incident light to diffract along the direction of micromirror switching, and result in light ‘leakage’ into the ‘on’ state even if the micromirror is in the ‘off’ state. This light diffraction decreases the contrast ratio of the micromirror.

Abstract: Apparatus are provided for fatigue testing ferroelectric material in a wafer, including an on-chip oscillator to provide a bipolar waveform to a ferroelectric capacitor formed in the wafer, as well as a switching system to selectively provide external access to the ferroelectric capacitor. Test methods are also disclosed provided, including measuring a performance characteristic of a ferroelectric capacitor in the wafer, providing a bipolar waveform to the ferroelectric capacitor for a number of cycles using an on-chip oscillator, and again measuring the performance characteristic after an integer number of cycles of the bipolar waveform.