Abstract: The invention provides tester load board shields for attachment to tester load boards. The shields of the invention protect from physical damage and electromagnetic interference. A preferred embodiment of a tester load board shield of the invention is disclosed in which a disc and outer rim of conductive metal such as aluminum or aluminum alloy are configured to accept a tester load board. The tester load board shield has holes to align with a selected tester load board for attachment of the shield thereto. Stanchions are provided to facilitate attachment of the Loadboard with shield to automatic test equipment known in the arts while a tester load board, also familiar in the arts, is fastened to the shield. Another embodiment of a tester load board shield is disclosed in the shape of annulus configured to contain a tester load board within an outer rim planar surface and inner rim.

Abstract: A semiconductor wafer design and process having test pads (36) reducing cracks generated during the wafer saw process from extending into and damaging adjacent die. The present invention provides a plurality of circular test pads (36) in a wafer scribe street (34) such that any cracks generated in the test pad during wafer saw self terminate in the periphery of the circular test pad. By providing a curved test pad periphery, cracks will tend to propagate along the edges of the test pads and self terminate therein. The circular test pads avoid any sharp corners as is conventional in rectangular test pads which tend to facilitate the extension of cracks from corners to extend into the adjacent wafer die (32). The present invention utilizes existing semiconductor fab processing and utilizes new reticle sets to define the curved test pads.

Abstract: An apparatus for effecting signal chopping in an amplifier device having an amplifier section, a modulation section, a ramp generating section and a clock section includes: at least one signal treating unit coupled among the clock section, the amplifier section and the ramp generating section. The at least one signal treating unit cooperates with the clock section to effect providing a chopping signal to the amplifying unit at a chopping frequency and to effect providing a ramping signal at a ramping frequency to the ramp generating section. The chopping frequency is neither a fundamental frequency nor a harmonic frequency of the ramping frequency.

Abstract: In accordance with an embodiment of the present invention an improved equalization system for DMT based modem receiver is provided. It includes a time domain equalizer for processing samples from an analog front end and includes a device for computing differences of time domain samples for every frame and the results are saved. An FFT is provided for calculating a first FFT and the results are saved in a FFT buffer so that at each DMT frame, after a difference and FFT operation, the FFT buffer contains the first FFT and v?1 time domain sample differences. A sliding FFT for each tone reads the first FFT result and v?1 FFTs and recursively computes the rest of v?1 FFTs for the particular tone. An equalizer is responsive to the computed sliding FFT for recursively computes equalizer outputs.

Abstract: A processor adapted to couple to external memory. The processor comprises a controller and data storage. The data storage is usable to store local variables and temporary data and is configurable to operate in either a cache policy mode in which a miss results in an access of the external memory or in a scratch pad policy mode in which a miss does not result in an access of the external memory. The data storage comprises first and second portions, and wherein only one of said portions is active at a time for storing said local variables. When the active portion does not have sufficient capacity for additional local variables, the other portion becomes the active portion for storing local variables. When one portion is the active portion, the other portion is used to store the temporary data and such other portion is sufficiently large to contain the temporary data.

Abstract: A clamping circuit containing a transistor and a current amplifier. The transistor is designed to turn on when the voltage at a node exceeds (falls below) a specified upper (lower) level. The current amplifier is designed to draw substantial amount of current when the transistor is turned on to clamp the voltage at the node to the desired level.

Abstract: In a method and system for fabricating a semiconductor device (100) having a package-on-package structure, a bottom laminate substrate (BLS) (130) is formed to include interconnection patterns (IP) (170, 172) coupled to a plurality of conductive bumps (PCB) (130). A top substrate (TS) (140) is formed to mount a top package (110) by forming a polyimide tape (PT) (142) affixed to a metal layer (ML) (144), and a top die (136) attached to the ML (144) on an opposite side as the PT (142). A laminate window frame (LWF) (150), which may be a part of the BLS (130), is fabricated along a periphery of the BLS (130) to form a center cavity (160). The center cavity (160) enclosed by the BLS, the LWF and the TS houses the top die (136) affixed back-to-back to a bottom die (134) that is affixed to the BLS (130). The IP (170, 172) formed in the BLS and the LWS (150) provide the electrical coupling between the ML (144), the top and bottom dies (136, 134), and the PCB (130).

Abstract: In a method and system for fabricating a semiconductor device (100) having a package-on-package structure, a bottom laminate substrate (BLS) (130) is formed to include interconnection patterns (170) coupled to a plurality of conductive bumps (130). A top substrate (TS) (140) is formed as a receptor to mount a top package (110). The TS (140) is formed by a polyimide tape (142) affixed to a metal layer (144). A laminate window frame (LWF) (150), which may be fabricated as a part of the BLS (130), is fabricated along a periphery of the BLS (130) to form a center cavity (160). The center cavity (160) that is enclosed by the BLS (130), the LWF (150) and the TS (140) houses at least one die (134, 136) attached to the BLS (130). The interconnection patterns (170, 172) formed in the BLS (130) and the LWF (150) provide the electrical coupling between the metal layer (144), the at least one die (134, 136), and the plurality of conductive bumps (130).

Abstract: A communication apparatus comprising an audio input device adapted to capture a first audio sample, where the first audio sample comprises a noise component. The apparatus further comprises signal processing logic coupled to the audio input device. If the intensity of the noise component is equal to or greater than the intensity of a voice component of a second audio sample received from a different communication apparatus, the signal processing logic amplifies the voice component.

Abstract: A wireless device (10, 12) is provided that distinguishes between multiple piconets. The wireless device (10, 12) includes a preamble component (160, 162, 164, 166) and a correlator (150) component. The preamble component (160, 162, 164, 166) provides a preamble (120) for a wireless fixed frequency interleaving transmission, and the correlator component (150) distinguishes a wireless transmission based on the preamble (120). A circuit (180) is provided for a wireless receiver to despread a hierarchical sequence (120) made by spreading an M-length sequence (110) with an N-length sequence (112). The circuit (180) includes a first and second despreaders (185, 190). The first despreader (185) is coupled to a signal input to despread a received signal. The signal is a fixed frequency interleaved transmission. The second despreader (190) is coupled to an output of the first despreader (185). The second despreader (190) despreads the output of the first despreader (185) with a second sequence.

Abstract: A system and method is described for saving power in a wireless network, using a physical layer address filtering protocol based on a partial address subset of the complete destination MAC address. The system comprises a PHY layer filtering protocol for generating the partial address and writing the partial address into a PHY layer header portion (e.g., PLCP header) of a sending station, or reading the partial address from the PHY layer header portion upon transmission of each frame. A receiving station receives and decodes these PHY layer header portion bits, in accordance with the protocol, and compares whether the subset of bits match that of the stations' own partial address. If a station finds a match, the station then continues further decoding the frame at PHY layer and send the complete frame to the MAC layer for further processing. The stations that do not have a match will not activate their MAC layer components.

Abstract: An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944) circuits. The scan paths apply stimulus test data to functional circuits (702) on the integrated circuit and receive response test data from the functional circuits. A scan distributor circuit (800) receives serial test data from a peripheral bond pad (802) and distributes it to each parallel scan path. A scan collector circuit (844) collects test data from the parallel scan paths and applies it to a peripheral bond pad (866). This enables more parallel scan paths of shorter length to connect to the functional circuits. The scan distributor and collector circuits can be respectively connected in series to provide parallel connections to more parallel scan paths. Additionally multiplexer circuits (886,890) can selectively connect pairs of scan distributor and collector circuits together.

Abstract: A protection circuit for protecting an integrated circuit pad 201 against an ESD pulse, which comprises a discharge circuit having an elongated MOS transistor 202 (preferably pMOS) in a substrate 205 (preferably n-type), said discharge circuit operable to discharge the ESD pulse to the pad, to ground 203. The embodiment further contains a pump circuit connected to the pad for receiving a portion of the pulse's current; the pump circuit comprises a component 221 determining the size of this current portion (for example, another transistor, a string of forward diodes, or a reverse Zener diode), wherein the component is connected to ground. A discrete resistor 222 (for example about 40 to 60?) is connected between the pad and the component and is operable to generate a voltage drop (about 0.5 to 1.0 V) by the current portion.

Abstract: The peripheral circuitry (350, 360, ESD, BH) of an integrated circuit die on a wafer is tested without physically contacting the bond pads of the die.

Abstract: A method of conserving power in a WLAN receiver is provided wherein processing tasks that need only to be operated for a brief period of time during the reception of a received packet are enabled only during the brief period of time. The enabling includes providing multiple power control signals that are controlled by a state machine for enabling and disabling the processing tasks.

Abstract: A system and method for using asymmetric companion codecs to establish and maintain a communication. A communication system endpoint replaces instances of a companion codec with the members of a group of all of the companion codecs for the endpoint and performs appropriate translations of compatible codecs to provide a communication between communication system endpoints.

Abstract: The present invention provides a method for forming an interconnect on a semiconductor substrate 100. The method includes forming an opening 230 over an inner surface of the opening 130, the depositing forming a reentrant profile near a top portion of the opening 130. A portion of barrier 230 is etched, which removes at least a portion of the barrier 230 to reduce the reentrant profile. The etching also removes at least a portion of the barrier 230 layer at the bottom of the opening 130.

Abstract: A semiconductor device has a leadframe with a structure made of a base metal (105), wherein the structure consists of a chip mount pad (302) and a plurality of lead segments (303). Covering the base metal are, consecutively, a continuous nickel layer (201) on the base metal, a layer of palladium on the nickel, wherein the palladium layer (203) on the chip side of the structure is thicker than the palladium layer (202) opposite the chip, and a gold layer (204) on the palladium layer (202) opposite the chip. A semiconductor chip (310) is attached to the chip mount pad and conductive connections (312) span from the chip to the lead segments. Polymeric encapsulation compound (320) covers the chip, the connections, and portions of the lead segments, but leaves other segment portions available for solder reflow attachment to external parts.

Abstract: A wire feed sensor guide, used in fabrication of semiconductor packages, guides a wire W from a wire source to a wire bonding location. The wire feed sensor guide has a unitary slider 1 that can be manually slid into and out of a fixed portion (2 or 2/3). Slider 1 has a slot SL that guides wire W, and includes a hole S for a sensor wire SW (such as optical fiber) that senses the position of wire W within the slot. Slider 1 also includes an air tube hole A that transmits air to urge wire W from a first position W1 toward a second position W2 during a wire bonding cycle. Advantageously, the unitary nature of the slider (including its air tube hole A and sensor wire hole S) ensure that the air blowing and wire position sensing processes do not require manual adjustment. Moreover, the end of the sensor wire is substantially protected from contamination by being substantially enclosed in the slider 1 and exposed only inside slot SL, thus increasing reliability.

Abstract: A method of reducing a likelihood that a die pad will be delaminated from a die in an integrated circuit die package for a structure design during an attachment of a heat sink member to the die pad using solder, is provided. A sample structure of the structure design is evaluated to determine whether a volume of last solidification for the solder is centrally located with respect to the die pad and is located at or near an interface of the solder and the die pad. If the last solidification volume is centrally located and is located at or near the interface of the solder and the die pad, and if the die pad is delaminated from the die, the structure design is modified so that less metal of the heat sink member is centrally located than before the modifying.