Abstract: Semiconductor devices and manufacturing methods therefor are disclosed, in which a drain-extended MOS transistor comprises a self-aligned floating region proximate one end of the transistor gate and doped with a first type dopant to reduce channel hot carrier degradation, as well as an oppositely doped first source/drain laterally spaced from the first end of the gate structure in a semiconductor body. The device may further comprise a resurf region doped to a lower concentration than the floating region to facilitate improved breakdown voltage performance. A method of fabricating a drain-extended MOS transistor in a semiconductor device is disclosed, comprising providing first dopants to a floating region in a semiconductor body, which is self-aligned with the first end of a gate structure, and providing second dopants to source/drains of the semiconductor body, wherein the first and second dopants are different.

Abstract: The self correcting scheme to match pull up and pull down devices includes: a first comparator for comparing a common mode signal to a high reference limit; a second comparator for comparing the common mode signal to a low reference limit; a first flip flop having an input coupled to an output of the first comparator; a second flip flop having an input coupled to an output of the second comparator; a counter having inputs coupled to the first and second flip flops; and a delay device controlled by an output of the counter, wherein the delay device provides a pull down control signal that is delayed relative to a pull up control signal.

Abstract: An amplifier includes a differential amplifier (10) having an input stage (20) for amplifying a differential input signal (Vin), and an output stage (6) coupled to the input stage (20) for producing and output signal (Vout). The input stage (20) includes main input circuitry (20A) for amplifying small-signal values of the input signal (Vin) and alternative input circuitry (20B) for amplifying the input signal (Vin) during conditions which cause thermal imbalance in the main input circuitry (20B). The input stage (20) includes switching circuitry (12) for coupling the input signal (Vin) to the main input circuitry (20A) during normal small-signal operating conditions and to the alternative input circuitry (20A) during large-signal operating conditions that cause thermal imbalance in the main input circuitry (20B).

Abstract: The invention generally provides a method of intelligent frequency hopping such as in Bluetooth and Home RF networks. The method (100) includes the acts of sampling a plurality of channels in a frequency band and identifying each channel as a good channels or a bad channel (110), determining the size of a good window and the size of a bad window (120), and assigning a plurality of good channels to a good window (130) and a plurality of bad channels to a bad window (140). Accordingly, the method increases the reliability and throughput of wireless networks.

Abstract: A compiler tool is provided to selectively solicit assistance from a programmer in order to improve optimization of code compiled by the compiler. As a program is being compiled, the compiler keeps track of the places where it could do better if it only knew certain information. The user is presented with one or more pieces of advice that each identify a problem that prevented the compiler from making a particular optimization due to not enough information and one or more suggestions as to how to provide additional information to the compiler. This list is generally filtered so that only a subset of missing information that has a high likelihood of leading to better performance is presented. Other missing information is not requested.

Abstract: A power supply has a plurality of switching regulators providing a like plurality of regulated output voltages. The oscillators of the switching regulators are synchronized with one another by a synchronization signal. A synchronization signal detector is provided on one or more of the switching regulators to shift the switching frequency of the oscillator to a lower frequency upon detection of a synchronization signal.

Abstract: When a RESET signal is generated in a target processor during a test procedure, a reset sync marker is generated in a program counter trace stream. The reset sync marker includes a plurality of packets, the packets identifying that the reset sync marker is the result of a RESET signal. The packets identify the program counter address at the time of the generation of the RESET signal and relate the reset sync marker to a timing trace stream. When the RESET signal is removed, a second (reset-off) sync marker is generated identifying the removal of the RESET signal, identifying the program counter address, and relating the second sync marker to the timing trance stream.

Abstract: An SRAM array with a dummy cell row structure in which the SRAM array is divided into segments isolated by a row pattern of dummy cells. The dummy cell structure provides a continuous cell array at the lower cell patterning levels. The SRAM array includes a first and second array block each including an SRAM cell having a first layout configuration, one or more of the dummy cells having a second layout configuration arranged along the row pattern associated with a wordline of the SRAM array, a first power supply voltage line connected to the first array block, and a second different power supply voltage line connected to the second array block. The first and second power supply voltage lines of the array blocks are further connected to the one or more dummy cells.

Abstract: A single chip, embedded symmetric multiprocessor (ESMP) having parallel multiprocessing architecture composed of identical processors includes a single program memory. Program access arbitration logic supplies an instruction to a single requesting central processing unit at a time. Shared memory access arbitration logic can supply data from separate simultaneously accessible memory banks or arbitrate among central processing units for access. The system may simulate an atomic read/modify/write instruction by prohibiting access to the one address by another central processing unit for a predetermined number of memory cycles following a read access to one of a predetermined set of addresses in said shared memory.

Abstract: A processor comprises decode logic that determines an instruction type for each instruction fetched, a first level cache, a second level cache coupled to the first level cache, and control logic operatively coupled to the first and second level caches. The control logic preferably causes cache linefills to be performed to the first level cache upon cache misses for a first type of instruction, but precludes linefills from being performed to the first level cache for a second type of instruction.

Abstract: A method of data processing is described for generating a screened bitmap in an adaptive manner. The page being printed is subdivided into a plurality of smaller areas, and the optimal screening method is selected based on the content of the data being processed. Areas of the page that primarily comprise of graphic elements and/or fonts are screened as part of the rendering process, while areas that are primarily continuous tone elements are screened as a secondary step after the rendering process.

Abstract: The operating range of joint additive and convolutive compensating method is extended by enhanced channel estimation procedure that adds SNR-dependent inertia and SNR-dependent limit on the channel estimate.

Abstract: A simplified comparator circuit (10) having hysteresis and lower power requirements for its implementation. The circuit (10) includes 2 minimum-sized MOSFETs (MN4, MN5) providing feedback from the circuit output to an input device (MN1) body to produce hystereis, requiring very little power. This invention is suitable for applications not requiring a precisely set hysteresis magnitude.

Abstract: A digital system is provided with a secure mode (3rd level of privilege) built in a non-invasive way on a processor system that includes a processor core, instruction and data caches, a write buffer and a memory management unit. A secure execution mode is thus provided on a platform where the only trusted software is the code stored in ROM. In particular the OS is not trusted, all native applications are not trusted. A secure execution mode is provided that allows virtual addressing when a memory management unit (MMU) is enabled. The secure execution mode allows instruction and data cache to be enabled. A secure execution mode is provided that allows all the system interruptions to be unmasked. The secure mode is entered through a unique entry point. The secure execution mode can be dynamically entered and exited with full hardware assessment of the entry/exit conditions. A specific set of entry conditions is monitored that account for caches, write buffer and MMU being enabled.

Abstract: A method of loading data into a spatial light modulator, in which a software programmable processor stores binary values for the pixels of at least a portion of the (x,y) array of a spatial light modulator. The processor stores these values in its addressable memory, and accesses them by calculating bit positions in memory words (elements), as a function of x and y and other parameters of the processor and spatial light modulator. The same concepts may be applied to reading data out of a spatial light modulator.

Abstract: In an integrated circuit receiving multiple serial data streams in parallel, a local clock is generated from each data stream and is synchronized with the data stream. Sometimes a data stream may have no transitions making it difficult to keep the clock synchronized with its data. A clock channel is provided, which always has edges. A circuit is provided for each data stream which measures the time elapsed since the data stream had an edge. After a certain period, the phase of the local clock is nudged towards that of the clock channel. Thereafter, the longer there are no edges on the data stream the more frequently nudges towards the phase of the clock channel are made.

Abstract: A circuit for receiving multiple serial datastreams in parallel is disclosed. A bit clock is recovered from each data stream, there being one data bit for ach transition of the clock signal both positive and negative going. The phases of the bit clocks are compared and are adjusted by 180 degrees so that the positive going edges of all occur close to each other. The bits of each stream are assembled into words under the control of a word clock. In one embodiment a common word clock is derived form the set of bit clocks as a whole. In another embodiment each stream is provided with its own word clock which is aligned to positive edges of the respective bit clocks that are close to each other.

Abstract: The invention provides a method of fabricating a semiconductive device [200]. In this embodiment, the method comprises depositing a hydrocarbon layer [294] over a semiconductive substrate, forming an interconnect structure [295, 297] within the hydrocarbon layer [294], and removing the hydrocarbon layer [294] by sublimation.

Abstract: A differential input comparator circuit comprises an input stage comprising dual polarity input voltages and an output stage adapted to output a differential voltage based on the input voltages, wherein the differential voltage is adapted to be transmitted to a comparator and wherein the circuit has high input impedance and works with high input voltage swings.

Abstract: This invention is a new CMOS voltage booster (20) having an output which can be used in memories to boost the word line voltage above VDD or other voltage boosting applications. The CMOS booster includes a NMOS FET (MN1) to charge a boosting capacitor (C1) to VDD at the end of each memory access and includes a PMOS FET (MP1, MP2) to keep the voltage at the output at VDD during standby. By using this combination, the word line rise time, the size of the booster, and the power consumption during access are significantly reduced. The gate of the NMOS FET (MN1) is boosted above VDD+Vthn by a small capacitor (C2) to charge the word line boosting capacitor to VDD at the end of each memory access. The small capacitor (C2) is pre-charged to VDD by a NMOSFET (MN2) whose gate is connected to the word line boosting capacitor. The gate of each PMOS FET (MP1, MP2) is shorted to its source to turn if off during boostenig. Transistor (MP3) facilitates boosting the NMOS FET (MN1) above VDD.