Abstract: A packaged micromechanical device (100) having a blocking material (116) encapsulating debris-generating regions thereof. The blocking material (116) prevents the generation of debris that could interfere with the operation of the micromechanical device (100). Debris-generating regions of the device (100), including debris-creating sidewalls and any debris-harboring cavities, as well as electrical connections (108) linking the device (100) to the package substrate (102) are encapsulated by the blocking material (116). The blocking material (116) avoids contact with any debris-intolerant regions (118) of the device (100). A package lid (124), which is glass in the case of many DMD packages, seals the device (100) in a package cavity (120).
Abstract: A transmit channel (gt1, h, gr2) through which a first wireless communication transceiver is to transmit to a second wireless communication transceiver can be estimated using information indicative of a relationship between the transmit channel and a receive channel (gt2, h, gr1) through which the first wireless communication transceiver receives communications from the second wireless communication transceiver. The relationship information (35) is combined (37) with further information (31) to produce an estimate of the transmit channel.
Type:
Grant
Filed:
December 5, 2003
Date of Patent:
June 12, 2007
Assignee:
Texas Instruments Incorporated
Inventors:
Henry S. Eilts, Srinath Hosur, David P. Magee
Abstract: A voltage generation circuit generates a reference voltage using a bandgap reference. A countering circuit is included to adaptively counter for any deviations caused in a bandgap reference voltage such that the reference voltage is independent of fabrication process variations and changes in ambient temperature. In an embodiment, current, proportionate to deviation in absolute value of Vbe from a nominal value, is injected into an emitter-base junction to cause Vbe to equal the nominal value.
Abstract: The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit. The method for manufacturing the semiconductor device, among other steps, includes forming a gate structure (130) over a substrate (110), the gate structure (130) having L-shaped sidewall spacers (430) on opposing sidewalls thereof and placing source/drain implants (310 or 510) into the substrate (110) proximate the gate structure (130). The method for manufacturing the semiconductor device further includes removing at least a portion of a horizontal segment of the L-shaped sidewall spacers (430).
Type:
Grant
Filed:
March 8, 2005
Date of Patent:
June 12, 2007
Assignee:
Texas Instruments Incorporated
Inventors:
Jong Shik Yoon, Shirin Siddiqui, Amitava Chatterjee, Brian E. Goodlin, Karen H. R. Kirmse
Abstract: A driver circuit includes a first transistor coupled between an input supply node and an output node. The first transistor operates in one of a conductive state to couple the output node with the input supply node and non-conductive state according to cooperative operation of a second transistor and a third transistor. The second transistor is coupled to provide a control input to drive the first transistor to the conductive state thereof in response a first input signal provided at a control input of the second transistor. The third transistor is coupled to provide an output at the output node in response to a second input signal provided at a control input of the third transistor, the first and second input signals being out of phase with each other. Circuitry is coupled between the input supply node and the control input of the first transistor to provide reduced impedance at the control input of the first transistor according to operation of the second transistor.
Type:
Grant
Filed:
April 22, 2005
Date of Patent:
June 12, 2007
Assignee:
Texas Instruments Incorporated
Inventors:
Siew Kuok Hoon, Franco Maloberti, Jun Chen
Abstract: An amplifier system can include a biasing amplifier that provides a first amplified signal to a DC blocking element that is connected with a load based on a first control signal. A power amplifier provides a second amplified signal for driving the load based on a second control signal. A control system controls the biasing amplifier to charge the DC blocking element so as to mitigate a voltage drop across the load (e.g., to substantially eliminate audible artifacts) when the power amplifier is activated to provide the second amplified signal.
Type:
Grant
Filed:
May 5, 2005
Date of Patent:
June 12, 2007
Assignee:
Texas Instruments Incorporated
Inventors:
Thomas Holm Hansen, Kim Nordtorp Madsen, Claus Niels Neesgaard
Abstract: A method for manufacturing an integrated circuit 10 having transistors 20, 30 of two threshold voltages where protected transistor stacks 270 have a gate protection layer 220 that are formed with the use of a single additional mask step. Also, an integrated circuit 10 having at least one polysilicon gate transistor 20 and at least one FUSI metal gate transistor 30.
Abstract: An embodiment of the invention is a method of cleaning a material stack 2 that has a hard mask top layer 8. The method involves cleaning the material stack 2 with a fluorine-based plasma etch. The method further involves rinsing the material stack 2 with a wet clean process.
Abstract: A system and method are provided that are operable for network communications that promote network devices to receive a transmit request, transmit a first part of a frame by a physical layer without a second part of the frame from a medium access control layer, and request the second part of the frame by the physical layer from the medium access control layer. These systems and methods also allow, in some embodiments, for the transmitting of the second part of the frame by the physical layer with data from the medium access control layer.
Abstract: The addition of DMD illumination modulator(s) 702 in series with projection SLM(s) 706/709 to produce high-performance projection displays with improved optical efficiency, reliability, and lower maintenance requirements. This approach eliminates the vibration, audible noise, and safety problems associated with high speed rotating color filter wheels 203 commonly used in SLM projectors and controls the light applied to individual areas of the projection SLM(s).
Abstract: One embodiment of the invention is a method for evaluating a material such as low-k dielectric, by a stress-generating test tool such as a needle. The evaluation object is shaped as a stack of adhering layers: low-k dielectric, first metal (preferably copper), barrier metal (preferably tantalum nitride), and second metal (preferably aluminum). A numerical correlation is established between a cracking in the barrier metal layer caused by probing and a damage in the layer of insulating material-to-be-tested. A predetermined number of locations of the top metal layer is selected for the probing step comprising touch-down, applying force, and lifting is repeated so that the number of repeats provide a pre-determined statistical confidence level.
Type:
Grant
Filed:
June 6, 2005
Date of Patent:
June 5, 2007
Assignee:
Texas Instruments Incorporated
Inventors:
Daniel J. Stillman, Nancy R. Ota, Cheryl Hartfield
Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS regions. A first oxide layer is formed in core and I/O regions of a semiconductor device (506). The first oxide layer is removed (508) from the core region of the device. A high-k dielectric layer is formed (510) over the core and I/O regions. Then, the high-k dielectric layer is removed (512) from PMOS regions of the core and I/O regions. A second oxide layer is formed (516) within NMOS regions of the core and I/O regions and a nitridation process is performed (518) that nitrides the second oxide layer and the high-k dielectric layer.
Type:
Grant
Filed:
April 29, 2005
Date of Patent:
June 5, 2007
Assignee:
Texas Instruments Incorporated
Inventors:
Luigi Colombo, James Joseph Chambers, Mark Robert Visokay
Abstract: A method and system in which a semiconductor wafer having a plurality of dies is inspected through a visual inspection and/or an electrical test. If certain of the dies on the wafer pass the inspection, then windows are mounted or affixed above those certain dies while they are still a part of the wafer.
Type:
Grant
Filed:
June 20, 2005
Date of Patent:
June 5, 2007
Assignee:
Texas Instruments Incorporated
Inventors:
Thomas A. Kocian, Richard L. Knipe, Mark H. Strumpell
Abstract: Semiconductor devices (102) and fabrication methods (10) are provided, in which a nitride film (130) is formed over NMOS transistors to impart a tensile stress in all or a portion of the NMOS transistor to improve carrier mobility. The nitride layer (130) is initially deposited over the transistors at low temperature with high hydrogen content to provide a moderate tensile stress in the semiconductor body prior to back-end processing. Subsequent back-end thermal processing reduces the film hydrogen content and causes an increase in the applied tensile stress.
Type:
Grant
Filed:
April 19, 2004
Date of Patent:
June 5, 2007
Assignee:
Texas Instruments Incorporated
Inventors:
Haowen Bu, Rajesh Khamankar, Douglas T. Grider
Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and a method for manufacturing an integrated circuit. The semiconductor device (100), among other possible elements, includes a first transistor (120) located over a semiconductor substrate (110), wherein the first transistor (120) has a metal gate electrode (135) having a work function, and a second transistor (160) located over the semiconductor substrate (110) and proximate the first transistor (120), wherein the second transistor (160) has a plasma altered metal gate electrode (175) having a different work function.
Type:
Grant
Filed:
April 16, 2004
Date of Patent:
June 5, 2007
Assignee:
Texas Instruments Incorporated
Inventors:
Husam N. Alshareef, Mark R. Visokay, Antonio Luis Pacheco Rotondaro, Luigi Colombo
Abstract: Semiconductor devices formed on wafers are inspected using a master wafer. A subject wafer of a semiconductor design is provided. The subject wafer has dies wherein semiconductor devices of the semiconductor design are formed and at a stage of fabrication. A current layer of the subject wafer is scanned to obtain a scanned layer/image. A master wafer comprising individual wafer/layer maps is obtained. The scanned layer is compared with a corresponding layer map. Matching and non-matching defects are identified from repetitive defects within the corresponding layer map and defects within the scanned layer. The matching defects are reviewed to classify and or identify causality. The master wafer is then updated.
Type:
Grant
Filed:
August 15, 2005
Date of Patent:
June 5, 2007
Assignee:
Texas Instruments Incorporated
Inventors:
Richard L. Guldi, Jae H. Park, Deepak A. Ramappa
Abstract: Disclosed are apparatus and methods for designing electrical contact for a bipolar emitter structure. The area of an emitter structure (106, 306, 400, 404) and the required current density throughput of an electrical contact structure (108, 308, 402, 406) are determined. A required electrical contact area is determined based on the required current density, and the electrical contact structure is then designed to minimize the required electrical contact area with respect to the emitter structure area.
Type:
Grant
Filed:
July 15, 2002
Date of Patent:
June 5, 2007
Assignee:
Texas Instruments Incorporated
Inventors:
Joe Trogolo, Tathagata Chatterlee, Lily Springer, Jeff Smith
Abstract: The present invention provides a complementary metal oxide semiconductor (CMOS) device, a method of manufacture therefor, and an integrated circuit including the same. The CMOS device (100), in an exemplary embodiment of the present invention, includes a p-channel metal oxide semiconductor (PMOS) device (120) having a first gate dielectric layer (133) and a first gate electrode layer (138) located over a substrate (110), wherein the first gate dielectric layer (133) has an amount of nitrogen located therein. In addition to the PMOS device (120), the CMOS device further includes an n-channel metal oxide semiconductor (NMOS) device (160) having a second gate dielectric layer (173) and a second gate electrode layer (178) located over the substrate (110), wherein the second gate dielectric layer (173) has a different amount of nitrogen located therein. Accordingly, the present invention allows for the individual tuning of the threshold voltages for the PMOS device (120) and the NMOS device (160).
Abstract: A separated synchronizing scrambler/descrambler pair that removes the possibility of catastrophic error due to improper transmission of initial condition information without disrupting the OFDM modulation scheme of a system that includes error-correction coding circuitry and replay variation. A transmitting device within the pair includes a first and a second data scrambler wherein the first data scrambler couples to receive the incoming data stream and filters the incoming data stream to provide a first filtered signal using a key signal. The second data scrambler, having an initial condition, couples to receive the first filtered signal and converts it into a scrambled signal using a scrambling seed. The second data scrambler comprises a random series generator for generating the scrambling seed to convert the first filtered signal into a scrambled signal. The scrambled signal is transmitted to the receiving device.