Patents Assigned to Integrated Device Technology
  • Patent number: 5325335
    Abstract: A sense amplifier for a static memory includes two pull-up transistors. The gate of each transistor is coupled to the drain of the other transistor. A circuitry is provided for precharging the drains of both pull-up transistors to a selected voltage such that by the start of the tracking stage of the amplifier, both pull-up transistors are off. If the tracking stage is long enough, one pull-up transistor turns on while the other one remains off, so that before the start of the sensing stage both pull-up transistors reach their final ON/OFF states. Hence the amplifier is fast and power efficient. The memory bit lines are precharged to VCC before the tracking stage, improving the read-disturb immunity and hence allowing a wider range of voltages on the bit lines and the sense amplifier inputs. The noise immunity and tolerance to temperature process variations are improved as a result. The high noise immunity make the amplifier and the memory suitable for integration with noisy circuits such as CPUs.
    Type: Grant
    Filed: June 5, 1992
    Date of Patent: June 28, 1994
    Assignee: Integrated Device Technology, Inc.
    Inventors: Michael A. Ang, David J. Pilling
  • Patent number: 5325487
    Abstract: A FIFO buffer includes a shadow register connected at the sense amplifier output of a dual port memory. The shadow register allows data to be read from the FIFO at an increased speed since the memory delay path is eliminated by preloading data into the shadow register.To support increased speed of the FIFO, a flag logic circuit is incorporated within the FIFO which asserts the full flag and the empty flag with minimal delay. The flag logic circuit is faster since delays due to comparison logic are eliminated.
    Type: Grant
    Filed: August 14, 1990
    Date of Patent: June 28, 1994
    Assignee: Integrated Device Technology, Inc.
    Inventors: Fu L. Au, Einat Yogev
  • Patent number: 5317711
    Abstract: A structure and a method are provided to bring internal signals of an integrated circuit to the external pins for monitoring purpose. In one embodiment, the signals on an internal bus between an on-chip cache and a CPU in a microprocessor are provided on the microprocessor's pins for a bidirectional data/address bus, when the bidirectional data/address bus is not used for data/address bus transactions with the main memory or the peripheral input/output devices. In this embodiment, reserved pins are used to selectively enable the address/data bus for bringing out the signals of the on-chip bus.
    Type: Grant
    Filed: June 14, 1991
    Date of Patent: May 31, 1994
    Assignee: Integrated Device Technology, Inc.
    Inventors: Philip A. Bourekas, Yeshayahu Mor, Scott Revak
  • Patent number: 5310700
    Abstract: A passive semiconductor structure for reduction of the mutual capacitance between parallel conductors, with two parallel conductors separated from a substrate by a first dielectric layer and covered by a second dielectric layer. The second dielectric layer having a cavity formed between these conductors, whereby the effective relative dielectric constant of the medium between these conductors is reduced.
    Type: Grant
    Filed: March 26, 1993
    Date of Patent: May 10, 1994
    Assignee: Integrated Device Technology, Inc.
    Inventors: Chuen-Der Lien, Jimmy J. Lee, Daniel J. L. Liao, Joe F. Santandrea
  • Patent number: 5306967
    Abstract: An apparatus for reducing signal degradation, propagation delay, and electromagnetic emission problems inherent in transmission of electrical signals along interconnect lines (such as lines which connect transistors in integrated circuits). The apparatus includes one or more pairs of generally parallel interconnect lines. Each line in each pair comprises line sections, and an inverter is connected between each pair of adjacent sections of each line. The inverters are arranged in staggered fashion, in the sense that the inverters connected along each line of a line pair are offset longitudinally from the inverters connected along the other line of the pair. Both bidirectional and unidirectional buses (groups of generally parallel interconnect line pairs) can be implemented in accordance with the invention.
    Type: Grant
    Filed: May 29, 1992
    Date of Patent: April 26, 1994
    Assignee: Integrated Device Technology, Inc.
    Inventor: Keith E. Dow
  • Patent number: 5284800
    Abstract: An embodiment of the present invention is a semiconductor fabrication process that deposits an oxide layer after a step to make contact openings in a BPSG layer and before a contact reflow step. The oxide allows implant dopants to be properly activated in the contact reflow step without excessive reflow of the BPSG.
    Type: Grant
    Filed: February 19, 1992
    Date of Patent: February 8, 1994
    Assignee: Integrated Device Technology, Inc.
    Inventors: Chuen-Der Lien, Daniel Liao, Jowei Dun
  • Patent number: 5260902
    Abstract: A redundancy system for a random access memory circuit includes a plurality of groups, each having first and second multiplexers on opposite sides thereof, each group being made up of two squads each containing four columns. Pairs of columns from one group are interlaced with pairs of columns of the other group.
    Type: Grant
    Filed: May 30, 1991
    Date of Patent: November 9, 1993
    Assignee: Integrated Device Technology, Inc.
    Inventors: David J. Pilling, Michael A. Ang, Scott Revak
  • Patent number: 5258317
    Abstract: An embodiment of the present invention is a process for semiconductor device having a silicon substrate. The process comprises positioning at least one field implant mask and field implanting a silicon substrate around a bipolar active region in a substrate such that boron atoms are blocked out of an active region, and only the field region surrounding said active area is implanted, said implanting such that a predetermined layout area of a semiconductor device does not need to be increased to compensate for a BV.sub.bso problem.
    Type: Grant
    Filed: February 13, 1992
    Date of Patent: November 2, 1993
    Assignee: Integrated Device Technology, Inc.
    Inventors: Chuen-Der Lien, Kyle W. Terrill
  • Patent number: 5250854
    Abstract: A method and apparatus for raising bitlines selectively to desired voltage levels. The circuit of the invention can be controlled to operate either in a first mode (for raising the bitlines selectively to relatively low voltage levels) or in a second mode (for raising the bitlines to desired higher voltage levels). The circuit of the invention has two branches, one of which includes a first (NMOS or bipolar) transistor and preferably also one or more resistors connected in series with a terminal (other than the gate or base) of the first transistor. The second branch includes a PMOS or NMOS transistor. When the PMOS (or NMOS) transistor of the second branch is switched off, the circuit's first branch operates as a bitline pull-up circuit (for raising a bitline selectively to relatively low voltage levels).
    Type: Grant
    Filed: November 19, 1991
    Date of Patent: October 5, 1993
    Assignee: Integrated Device Technology, Inc.
    Inventor: Chuen-Der Lien
  • Patent number: 5228106
    Abstract: An amplifier of the present invention is suitable for use as sense amplifier in memories. Some embodiments of the amplifier are simple, fast and consume little power. A memory using the amplifier is also provided.
    Type: Grant
    Filed: May 30, 1991
    Date of Patent: July 13, 1993
    Assignee: Integrated Device Technology, Inc.
    Inventors: Michael A. Ang, David J. Pilling
  • Patent number: 5223443
    Abstract: An embodiment of the present invention is a method for determining the cleanliness of a semiconductor wafer initially deposited with polysilicon, patterned with photoresist, processed, and then having the resist removed under standard conditions. The method comprising the steps of: depositing a thin TEOS film over the entire surface of a wafer; exposing said wafer to a solution of hot potassium hydroxide (KOH) that attacks polysilicon and is highly selective to and does not etch said TEOS film, the exposing such that if any pin hole exists in the TEOS film an underlying layer of polysilicon is attacked vigorously; and inspecting said wafer for a visual indication in said polysilicon layer of whether or not said polysilicon layer was attacked by the exposure to said potassium hydroxide (KOH).
    Type: Grant
    Filed: February 19, 1992
    Date of Patent: June 29, 1993
    Assignee: Integrated Device Technology, Inc.
    Inventors: Jeffrey D. Chinn, Ciaran P. Hanrahan
  • Patent number: 5199002
    Abstract: For enabling a static, random-access-memory (500) bit lines (556 and 558) pre-charging circuit (518), employed is an address-change-detection circuit (510) having a plurality of address-change-detectors (570 and 572) each for detecting a change in an associated SRAM addressing signal and, driven by the address-change detectors (570 and 572), a pulse generator (700) driving the pre-charging circuit (518).
    Type: Grant
    Filed: October 1, 1990
    Date of Patent: March 30, 1993
    Assignee: Integrated Device Technology, Inc.
    Inventors: Michael A. G. Ang, Kevin W. Glass, David J. Pilling
  • Patent number: 5182475
    Abstract: An improved circuit for translating ECL level voltages to CMOS level voltages. The circuit of the invention has a voltage gain stage with a bipolar transistor connected to a PMOS transistor, and a resistive loading stage including NMOS transistors. The bipolar transistor functions to increase the speed of the circuit (particularly at high temperatures) by increasing the driving capability of the voltage gain stage. The speed of the circuit will degrade very little at high temperature and high output load conditions, because the current driving capability of the bipolar transistor employed has low sensitivity to output loading and temperature.
    Type: Grant
    Filed: September 20, 1991
    Date of Patent: January 26, 1993
    Assignee: Integrated Device Technology, Inc.
    Inventor: Chuen-Der Lien
  • Patent number: 5175819
    Abstract: A parallel-to-serial FIFO buffer device (100) employs a FIFO buffer (110) for storing words of data; a tap-shift-register portion (112); and a data-shift-register portion (116) for converting from parallel to serial format words of data stored in the FIFO buffer (110), tap-shift-register portion (112) controls the conversion process, receives (150) a serial-input-expansion (RSIX) input signal, and develops (170) a serial-output-expansion (RSOX) output signal. The serial-input-expansion input signal (150) and the serial-output-expansion output signal (170) permit the device (100) to be connected with one, or more, similar, device(s) for word length and/or depth expansion.
    Type: Grant
    Filed: March 28, 1990
    Date of Patent: December 29, 1992
    Assignee: Integrated Device Technology, Inc.
    Inventors: Danh Le Ngoc, Fulam Au, John R. Mick
  • Patent number: 5175859
    Abstract: A method of programming a cache tag comparator by designing a semiconductor device's internal circuitry such that an input/output pin of the device may be programmed by an external resistor to ground that will indicate during the reset phase of the device that an alternate function for the pin is to be selected or that the pin itself is to be disabled.
    Type: Grant
    Filed: May 1, 1990
    Date of Patent: December 29, 1992
    Assignee: Integrated Device Technology, Inc.
    Inventors: Michael J. Miller, Philip A. Bourekas, Avigdor Willenz
  • Patent number: 5173627
    Abstract: The invention provides an output enable control circuit with a three gate delay. The circuit includes a CMOS passgate or other transmission control and filtering means, one or more shunting transistors, and an output driver. The CMOS passgate, in conjunction with a first shunting transistor, allows an output enable command to control transmission of the data signal to the output driver. By properly tuning the CMOS passgate, bounce on the power supply and ground lines can be minimized. A second shunting transistor can be included to allow other data control signals, such as a write enable or chip select signal, to cease data output by the circuit. Additionally, a third shunting transistor, controlled by the data signal, can be included to allow fast turn off of the output driver.
    Type: Grant
    Filed: July 17, 1991
    Date of Patent: December 22, 1992
    Assignee: Integrated Device Technology, Inc.
    Inventor: Chuen-Der Lien
  • Patent number: 5128731
    Abstract: A P/N-MOS transistor having source and drain of opposite semiconductor types is provided. One embodiment of the P/N-MOS transistor has turn-off characteristic similar to a PMOS transistor, and turn-on characteristic similar to a PMOS transistor connected in series with a p-n junction diode. An application of the P/N-MOS transistor is provided in a static random access memory (SRAM) cell. This SRAM cell has density advantage over SRAM cells using polysilicon PMOS transistors as active transistors.
    Type: Grant
    Filed: June 13, 1990
    Date of Patent: July 7, 1992
    Assignee: Integrated Device Technology, Inc.
    Inventors: Chuen-Der Lien, Fu-Chieh Hsu, Jeong Y. Choi, Jeng-Jiun Yang
  • Patent number: 5126975
    Abstract: An integrated cache memory device using SRAM cells is disclosed. The integrated cache memory has synchronized write capability and burst read capability.
    Type: Grant
    Filed: October 24, 1990
    Date of Patent: June 30, 1992
    Assignee: Integrated Device Technology, Inc.
    Inventors: James E. Handy, Kelly A. Maas
  • Patent number: 5099481
    Abstract: A serial protocol register and an initialization counter are configured to initialize (program) a RAM array. The register is configured to receive, in serial format, an initial address to be loaded into the counter. Also, the register is configured to receive, in serial format, a series of machine states (data words), each to be stored in the RAM array. In addition, the register is configured to clock the counter following each received machine state. The counter is configured to develop a series of addresses, each for accessing the RAM array to store in the array a corresponding one of the machine states.
    Type: Grant
    Filed: February 28, 1989
    Date of Patent: March 24, 1992
    Assignee: Integrated Device Technology, Inc.
    Inventor: Michael J. Miller
  • Patent number: 5086365
    Abstract: For electrostatic-discharge-protection, a first transistor is configured with the transistor channel connected between circuit ground and an associated (input or output) pad. In addition, transistors(s) are included configured to "float" the gate and/or the well of the first transistor when no power supply potential (Vcc) is present and to couple to circuit ground (or the power supply potential) the gate and/or the well of the first transistor when the normal power supply potential (Vcc) is present.
    Type: Grant
    Filed: May 8, 1990
    Date of Patent: February 4, 1992
    Assignee: Integrated Device Technology, Inc.
    Inventor: Cheun-Der Lien