Abstract: A conductive shield on the surface of an integrated circuit package improves the circuit and package performance. The conductive shield in the vicinity of the leads reduces lead inductance, thus increasing the frequency range of the package and reducing switching induced noise in digital circuits. The shield also blocks radio energy from entering or leaving the package through shielded area.

Abstract: A circuit improves the reliability of antifuses in certain types of systems by substantially eliminating the continuous undesirable applications of voltages across antifuse terminals. To accomplish this, an antifuse has applied across its two terminals a "reading" or "evaluation" voltage as required by the system operation for a single read or evaluation clock period (typically 5 ns to 30 ns in duration). The signal describing the state of the antifuse is then stored in a latch, register, or other suitable structure for subsequent sampling. In this manner, a low read current flows in the antifuse in response to the standard chip operating voltage for only a short period of time such as a single clock cycle. Thus, continuous voltages across the two terminals of the antifuse are avoided and an unprogrammed antifuse is not inadvertently programmed and a programmed antifuse is not inadvertently converted back to its high impedance state (i.e. "unprogrammed").

Abstract: A method forms, in a CMOS semiconductor substrate, P- and N-wells having independently optimized field regions and active regions. In one embodiment, P- and N-wells are formed by (i) creating in successive steps the field regions of the P- and N-wells; (ii) creating an oxide layer over the field regions, (iii) creating in successive steps the active regions. The method achieves the P- and N-wells without increasing the number of photoresist masking steps. In addition, optical alignment targets (OATs) are optionally formed simultaneously with these P- and N-wells without increasing the total number of process steps.

Abstract: An antifuse redundancy circuit operates with transparency to external circuitry and users. In one embodiment, an antifuse redundancy circuit incorporates two antifuses rather than one. The circuit is arranged so that both antifuses may be simultaneously programmed and read. If a single antifuse is programmed without programming the other antifuse, the antifuse redundancy circuit will register a programmed antifuse. Additionally, if a single programmed antifuse is unintentionally deprogrammed after both antifuses in the redundancy circuit have been programmed, the antifuse redundancy circuit will continue to register a programmed antifuse. The result is both an increase in manufacturing yield and an increase in the reliability of integrated circuits utilizing antifuses.

Abstract: The process parameters according to which the AMT 8310 RIE plasma etcher operates are altered so as to increase the nitride to oxide selectivity of the AMT 8310 RIE plasma etcher from approximately 3:1 to approximately 5:1, thereby allowing for the fabrication of modern semiconductor devices having oxide films significantly less thick than 325 .ANG.. In this manner, the present invention eliminates the need for an expensive upgrade in etching equipment to realize an increase in nitride to oxide selectivity. The semiconductor device is electrically biased at 100-300 volts, and freon and oxygen have a flow rate ratio of approximately 1:1.

Abstract: A plurality of parallel single port memory arrays are coupled between a corresponding plurality of input FIFO sets and a corresponding plurality of output FIFO sets to create a high-speed FIFO memory device. The input FIFO sets, which provide data values to their corresponding single port memory arrays, are responsive to a write clock signal. The output FIFO sets, which receive data values from their corresponding single port memory arrays, are responsive to a read clock signal. The order of read and write operations within each single port memory array is controlled by a corresponding state machine which is coupled to either the write clock signal or the read clock signal. Each of the parallel single port memory arrays operates independently. The input FIFO sets de-interleave an input data stream into a plurality of intermediate data streams. Each intermediate data stream is routed through a single port memory array to an output FIFO set.

Abstract: A method for forming a via in an integrated circuit having a reduced contact resistance. The integrated circuit includes a photoresist layer, an oxide layer, an etch stop layer and a metal layer. In one embodiment, a portion of the photoresist layer is removed to expose the underlying oxide layer, after which a portion of the oxide layer is removed to expose the underlying etch stop layer. A portion of the etch stop layer is then removed using a reactive ion etch-downstream microwave ash system under conditions that are effective to create a substantially water-soluble polymer residue within the via, to expose a portion of the underlying metal layer. The water-soluble polymer is then removed to expose the underlying metal layer.

Abstract: An output driver including pull-up and pull-down output transistors is formed in a silicon substrate. The source and the drain of the pull-up output transistor are formed in a common bulk region of the substrate. A bulk potential control circuit for controlling the voltage of the bulk region, a resistive element and a gate drive control circuit are also formed in the silicon substrate. A layer of interconnect formed over a top surface of the silicon substrate may selectively couple into the output driver circuit one or more of the resistive element between a source of the pull-down output transistor and a reference voltage source, the bulk potential control circuit to control the voltage of the bulk region of the silicon substrate, and the gate drive control circuit to control the rate of change of voltage on the gate of the pull-down transistor as a function of the voltage on this gate.

Abstract: A process for fabricating a CMOS structure using a single masking step to define lightly-doped source and drain regions for both N- and P-channel devices. The process forms disposable spacers adjacent to gate structures and at least one retrograde well. Retrograde wells are formed using one or more charged ions at different energy levels. In addition, heavily-doped source and drain regions are formed using blanket implants of two different conductivities into a semiconductor substrate having two contiguous wells of opposite conductivity type. By blanket implanting a first dopant into both wells, and then selectively implanting a second dopant, the diffusion of the second dopant is partially suppressed by the first dopant. The partial suppression of first dopant results in shallow implants being formed. Also disclosed is a process for forming contact openings and contact implants.

Abstract: A BiCMOS process is provided for fabricating on the same semiconductor substrate three types of N-wells optimized respectively for (i) PMOS FETs requiring low P+/N-well capacitance; (ii) NPN bipolar transistors which do not require low collector-to-substrate capacitance and PMOS FETs which require latch-up immunity; and (iii) NPN bipolar transistors which require low collector-to-substrate capacitance.

Abstract: A structure and a method are provided for refilling a block of memory words stored in a cache memory. The structure and method provide a read buffer to optimally match the processor speed with the main memory using read clock enable RdCEn and acknowledge (Ack) signals. The RdCEn signal is provided as each memory word is available from the main memory. The Ack signal is provided to indicate the time at which the processor may empty the read buffer at the processor clock rate without subsequently executing a wait cycle to wait for any remaining memory words in the block to arrive. The benefit of the present invention is obtained without incurring a performance penalty on the single word read operation.

Abstract: A circuit and method for protecting an integrated circuit during positive and negative ESD events. During both positive and negative ESD events, the circuit conducts ESD current through a turned on device. The circuit includes a pad, a voltage supply rail, a field effect transistor connected across the pad and the voltage supply rail, and an enabling circuit connected across the gate of the field effect transistor and the pad. During a positive ESD event, the field effect transistor is turned on to provide a conductive path between the pad and the voltage supply rail. During a negative ESD event, the bipolar transistor inherent in the field effect transistor is turned on to provide a conductive path between the pad and the voltage supply rail.

Abstract: A high capacitance field effect transistor for use in an integrated memory circuit is fabricated with an optimized gate electrode and active region overlap, increasing the gate electrode to substrate capacitance thereby minimizing the effect of alpha particle upset. The optimized overlap is accomplished by maximizing the opening in the field oxide layer which defines the active region. In some embodiments, the transistor is also optimized for overall cell layout area.

Abstract: Spacers are formed on the inside walls of a narrow silicon loss trench of a poly-emitter type bipolar transistor structure so that at most a narrow strip on the bottom of the trench receives high concentration doping when an extrinsic base region of the bipolar transistor is being doped. The narrowness of the exposed silicon surface which is etched to form the silicon loss trench slows vertical etching and thereby facilitates the formation of a shallow trench. The narrowness of the strip on the bottom of the trench which receives high concentration doping causes slow vertical diffusion of dopants. As a result, the highly doped link region which extends downward from the bottom of the trench does not extend downward much farther than the base region. A high cutoff frequency is therefore achievable by reducing the distance between the bottom of the base region and the top of the buried layer without decreasing the base-to-collector breakdown voltage.

Abstract: A structure and a method for directing execution of instructions are provided in a microprocessor with an on-chip cache memory. In one embodiment, the microprocessor provides a debug mode, which is activated by a signal on a mode pin. In the debug mode, when a signal is received on a second mode pin indicating that an instruction is to be provided on the memory bus is desired, a cache miss is generated at the next instruction fetch. Thus, the processor is forced to fetch the next instruction from main memory. The instruction is then provided on the memory bus as though it is fetched from the main memory in response to the read cycle resulting from the cache miss.

Abstract: A non-destructive method of identifying a type of molding compound in a sample using an acoustic microscope, particularly, identifying the type of molding compound used in an integrated circuit package by comparing attributes of the tested molding compound with known attributes of standard molding compounds to identify the molding compound being evaluated. The attributes that are compared include voltage, attenuation, peak frequency, average frequency, and the velocity of reflected sound.

Abstract: A fast fill method and apparatus for an instruction queue within a pipeline processor is provided. An instruction queue is placed between a translator and an instruction register within a pipeline processor to reduce holes or bubbles in the pipeline resulting from either the fetch stage or the translate/decode stage. The instruction queue is fast filled by the translator by providing multiple micro instructions from the translator, in parallel to either or both of the instruction queue and the instruction register. Queue store control logic is provided to manage sequencing of micro instructions between the translator, the instruction queue, and the instruction register.

Abstract: A redundancy circuit for a semiconductor memory device utilizes a fuse ladder comprising alternating programmable resistive fuses and signal restorers connected to one another in series. The signal restorers coupled between the fuses prevent the formation of a high impedance resistive line with a floating node when one of the fuses in the ladder is blown.

Abstract: A semiconductor capacitor used to test for contaminants in a fabrication line is created by: forming a layer of insulating material on a semiconductor substrate, forming a layer of conductive thin film on the layer of insulating material, and laser patterning an area of the conductive thin film. Laser patterning is performed by applying the laser along the outer boundary of the area to be patterned to energetically remove the conductive thin film along this boundary.

Abstract: A hysteresis circuit comprises a first logic section, a second logic section cascaded with the first logic section, and circuitry for controlling hysteresis threshold voltages of the hysteresis circuit. The hysteresis controlling circuitry conducts current from a source of a first supply voltage to the output lead of the first logic section during a low-to-high transition of an input voltage on an input terminal of the hysteresis circuit. The hysteresis controlling circuitry conducts current from the output lead of the first logic section to a source of a second supply voltage during a high-to-low transition of the input voltage on the input terminal of the hysteresis circuit. A clock generator integrated circuit chip employing the hysteresis circuit in a voltage controlled oscillator can generate squarewave signals of 150 MHz onto a plurality of output terminals when powered from approximately 3.3 volts throughout a 0 to 70 degree Celsius temperature range, a clock skew of less than 0.