Patents Assigned to Intel Corp.
  • Patent number: 8959531
    Abstract: Systems and methods of managing break events may provide for detecting a first break event from a first event source and detecting a second break event from a second event source. In one example, the event sources can include devices coupled to a platform as well as active applications on the platform. Issuance of the first and second break events to the platform can be coordinated based on at least in part runtime information associated with the platform.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: February 17, 2015
    Assignee: Intel Corp
    Inventors: Ren Wang, Jr-Shian Tsai, Tsung-Yuan C. Tai, Mesut A. Ergin, Prakash N. Iyer, Bruce L. Fleming
  • Patent number: 7406715
    Abstract: An environment for remote monitoring of a device, such as a child's computer, from a television or other monitor device. The monitored device has a security layer, which may be implemented in hardware, software, or a combination of the two, where the security layer inspects some or all accessed network data or network access activities, including real-time content such as chat rooms and the like. While the monitored device is used to access network data, alerts are displayed on the remote monitoring device to allow an adult or other responsible entity to keep track of material. Thus, for example, an adult may watch television, confident that an alert will be displayed in a corner of the television screen if necessary to alert the adult to any problems. For serious alerts, the security layer may automatically block or shutdown offending network application programs.
    Type: Grant
    Filed: March 19, 2003
    Date of Patent: July 29, 2008
    Assignee: Intel Corp.
    Inventor: Edward O. Clapper
  • Patent number: 7380136
    Abstract: Methods and apparatus for secure collection and display of user interface information in a pre-boot environment are disclosed. A disclosed system executes trusted software under a secure mode of a processor. In the secure mode, the processor may directly access an area of memory that normally cannot be accessed. One or more software routines, device drivers, digital certificates, hash codes, encryption keys, and/or any other data may be stored in the secure area of memory. Software routines and device drivers stored in the secure area of memory and/or certified by data in the secure area of memory may be “trusted.” Preferably, trusted software routines and/or device drivers are digitally signed by a trusted source (e.g., Microsoft). In addition to trusted interface objects, the pre-boot environment may include non-trusted interface objects. These non-trusted interface objects may use third party software routines and/or device drivers.
    Type: Grant
    Filed: June 25, 2003
    Date of Patent: May 27, 2008
    Assignee: Intel Corp.
    Inventors: Vincent J. Zimmer, Michael A. Rothman
  • Patent number: 7375288
    Abstract: In some embodiments, apparatuses and methods for improving ball-grid-array solder joint reliability in printed circuit boards. Such apparatuses may comprise, in an exemplary embodiment, a stiffened printed circuit board defining one or more cavities therein and including one or more stiffening members positioned, respectively, in the one or more cavities. The cavities and embedded stiffening members may be located proximate a ball-grid-array device footprint so as to resist deflection caused by the application of forces to the board by test probe pins during testing. Such methods may include, in an exemplary embodiment, creating one or more cavities in a middle sub-layer of a core layer of a stiffened printed circuit board and inserting one or more stiffening members, respectively, therein. Top and bottom sub-layers may then be secured to top and bottom surfaces of the middle sub-layer to complete the core layer. Other embodiments are also described and claimed.
    Type: Grant
    Filed: July 30, 2004
    Date of Patent: May 20, 2008
    Assignee: Intel Corp.
    Inventors: Sheng Cheang Ch'ng, Azizi Abdul Rakman, Teik Sean Toh
  • Patent number: 7263544
    Abstract: In particular, the present invention relates to a method and system for improving the efficiency of computational processes and specifically multiply and accumulate (“MAC”) processes such as the DCT (“Discrete Cosine Transform”) and/or IDCT (“Inverse Discrete Cosine Transform”) using a performance optimized method and associated hardware apparatus.
    Type: Grant
    Filed: January 18, 2006
    Date of Patent: August 28, 2007
    Assignee: Intel Corp
    Inventors: Yan Hou, Hong Jiang, Kam Leung
  • Patent number: 7171543
    Abstract: Apparatus and methods to execute an instruction of an application of a first bit size ported to a second bit size environment, including methods and apparatus to confine the application to a first bit size address space subset. An embodiment in accordance with the present invention includes a method to confine an application to an address space subset, the method including determining that the application is confined to a first bit size address subset, the application including an instruction; generating an address reference of a second bit size as part of execution of the instruction; truncating the generated address reference from the second bit size to the first bit size; and extending the truncated, generated address reference from the first bit size to the second bit size based at least in part on an address format control flag.
    Type: Grant
    Filed: March 28, 2000
    Date of Patent: January 30, 2007
    Assignee: Intel Corp.
    Inventors: Ronny Ronen, Alexander Peleg
  • Patent number: 6622212
    Abstract: In an example embodiment, an adaptive method of prefetching data blocks from an input/output device comprises predicting the address of each read operation reading a data block from the input/output device, the prediction based on the address of the immediately preceding read operation from the input/output device; tracking, for each read operation, whether each read operation reads a block data from the same address of the input/output device predicted for the read operation; and prefetching a data block for a read operation from the input/output device in accordance with the state of a state machine, the state of the state machine depending upon whether immediately preceding read operations read a data block from the same address of the input/output device predicted for the read operations.
    Type: Grant
    Filed: May 24, 1999
    Date of Patent: September 16, 2003
    Assignee: Intel Corp.
    Inventor: Raymond S. Tetrick
  • Patent number: 6550055
    Abstract: A method and device are provided for creating an information report for a computer system. An information report is used to signal a problem with a computer system and to provide information about the problem. The information report contains only relevant information, thereby decreasing the bandwidth required to send the information report, and the time required for a technician to review the information report. Information about the problem with the computer system is input by a user of the computer system. This information, together with information stored in a diagnostic tree, is used to limit the scope of an automatic information retrieval. An information report is produced from the results of the automatic information retrieval.
    Type: Grant
    Filed: December 29, 1998
    Date of Patent: April 15, 2003
    Assignee: Intel Corp.
    Inventors: Paul M. Cohen, Joseph R. Kluck, William J. Nerenberg, David E. Dent, Sanjay V. Vora
  • Patent number: 6509780
    Abstract: A technique for compensating a characteristic, such as a resistance, of at least one circuit includes selectively incrementing a characteristic of a dummy circuit and comparing it with a characteristic of an external reference to generate a reference code. A previous reference code is stored and subsequently compared with a present reference code. It is ensured that the present reference code differs by no more than a predetermined amount from the stored previous reference code by ceasing the incrementing or decrementing of the characteristic of the dummy circuit and utilizing the present reference code to compensate the characteristic of the at least one circuit.
    Type: Grant
    Filed: September 10, 2001
    Date of Patent: January 21, 2003
    Assignee: Intel Corp.
    Inventors: Chee How Lim, Usman Azeez Mughal
  • Patent number: 6456146
    Abstract: A system and method are presented for multiplexing two or more clocking signals. In one embodiment, a first enable circuit is provided that receives a select signal, a first clocking signal, and an enable signal from a second enable circuit. The first enable circuit generates an enable signal in response to these signals. For example, the first enable circuit could include a flip-flop clocked by the first clocking signal that generates the enable signal when the first clocking signal has been selected (based on the select signal), when the enable signal from the second enable circuit is deasserted and the first clocking signal has reached a falling edge. The enable signal can then be used to filter the first clocking signal (e.g., using an AND gate) to provide the first clocking signal as an output signal. Using the system and method of the present invention, glitches and spikes seen when multiplexing two or more clocking signals can be avoided.
    Type: Grant
    Filed: December 28, 2000
    Date of Patent: September 24, 2002
    Assignee: Intel Corp.
    Inventors: Nathanel Darmon, Aviad J. Wertheimer
  • Patent number: 6449327
    Abstract: A system and method are presented for providing a multi-stage counter. In one embodiment, a signal propagates from the most significant bit of the counter to the least significant bit of the counter that indicates that all “more significant” stages of the counter have reached a limit value (e.g., all 1's). Use of this propagating signal means that only the first (or first couple) stages of the counter are time critical, while the remainder are less so. The described counter may have a modular design and may result in lower power consumption.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: September 10, 2002
    Assignee: Intel Corp.
    Inventor: Eitan Emanuel Rosen
  • Patent number: 6401172
    Abstract: A method of processing a data request in a processing agent. The method comprises posting the data request internally within the agent and, if the data request implicates data associated with a pending external transaction, canceling and recycling the data request.
    Type: Grant
    Filed: December 18, 1998
    Date of Patent: June 4, 2002
    Assignee: Intel Corp.
    Inventors: Chinna Prudvi, Derek T. Bachand, David L. Hill
  • Patent number: 6397297
    Abstract: A computer system having cache modules interconnected in series includes a first and a second cache module directly coupled to an address generating line for parallel lookup of data and data conversion logic coupled between the first cache module and said second cache module.
    Type: Grant
    Filed: December 30, 1999
    Date of Patent: May 28, 2002
    Assignee: Intel Corp.
    Inventors: Zeev Sperber, Jack Doweck, Nicolas Kacevas, Roy Nesher
  • Patent number: 6381148
    Abstract: A processor retention assembly is disclosed. An embodiment of the processor retention assembly includes a first dual processor retention module and a second dual processor retention module. A connecting member is attached to the first dual processor retention module at a first end and is attached to the second dual processor retention module at a second end. In accordance with another embodiment of the present invention, covers are hingedly attached to each of the first and second dual processor retention modules.
    Type: Grant
    Filed: December 9, 1998
    Date of Patent: April 30, 2002
    Assignee: Intel, Corp.
    Inventors: George Daskalakis, Conal O'Neill, James Roecker
  • Patent number: 6381693
    Abstract: A system, a method of operating the system and a system firmware. The system includes a processor and a system firmware including a plurality of customized firmware parts, with each firmware part performing system firmware functions required for and customized to only a subset of a plurality of types of processors which are operational when connected to the system, and a processor identification device, coupled to the system, which identifies which subset of the plurality of types of processors is connected to the system and in response to the identification of the type of connected processor, causes a customized firmware part corresponding to the identified types of processor to be executed by the processor.
    Type: Grant
    Filed: December 31, 1998
    Date of Patent: April 30, 2002
    Assignee: Intel Corp.
    Inventors: Andrew J. Fish, William J. Clem
  • Patent number: 6373553
    Abstract: An optical lithography system and method which utilizes a mask pattern and forms Talbot sub-images of an illuminated grating onto a photosensitive target to print an image pattern on the photosensitive target such that the image pattern printed has a pitch equal to half the pitch of the mask pattern.
    Type: Grant
    Filed: September 20, 1999
    Date of Patent: April 16, 2002
    Assignee: Intel Corp.
    Inventor: Vivek K. Singh
  • Patent number: 6346743
    Abstract: A capacitor assembly having one or more capacitors embedded in the core layer of a package having integrated circuits (ICs) mounted thereon. Each embedded capacitor has plural pairs of first and second electrodes and the package core layer has plural sets of first and second vias dispersed over the pairs of electrodes and being connected thereto. A metal layer is provided on the core layer and includes a first portion having at least one metal strip and a second portion, electrically isolated from each strip. Each metal strip is positioned such that it is extended to overlie both the first electrode of a distinct pair of electrodes and the second electrode of an adjacent, succeeding pair of electrodes and effects a mutual electrical connection between them through first and second vias associated therewith, respectively.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: February 12, 2002
    Assignee: Intel Corp.
    Inventors: David G. Figueroa, Yuan-Liang Li, Chee-Yee Chung
  • Patent number: 6266773
    Abstract: A computer security system and method. An event detector detects events occurring in a monitored computer system, such as processor events, input events, and output events. A permission category list lists permission categories for events that might occur in the monitored computer system, and a decision maker determines action to be taken in response to detection of the event, based on the permission category of the event. The event detector might include an event list listing events to be detected, and the decision maker might include an action list listing action to be taken in response to different permission categories. If an event is not on the permission category list, the decision maker prohibits performance of the event, or alternatively issues a prompt to the computer user to specify action to be taken.
    Type: Grant
    Filed: December 31, 1998
    Date of Patent: July 24, 2001
    Assignee: Intel. Corp.
    Inventors: Gregory H. Kisor, Richard C. Calderwood
  • Patent number: 6256673
    Abstract: A client/server network system is disclosed for cyclic multicasting of an image file from a central data provider (server) to one or more remote client machines (workstations) over a computer network with minimum network transmission while allowing any number of client machines (workstations) to download the image file at any moment in time without the need to synchronize with the central server's transmission. The network system includes a computer network; a plurality of remote client machines on the computer network; and a central server for providing a cyclic multicasting of an image file to one or more client machines over the computer network concurrently through the use of different transmission cycles of a single cyclic multicast session.
    Type: Grant
    Filed: December 17, 1998
    Date of Patent: July 3, 2001
    Assignee: Intel Corp.
    Inventor: Jason A. Gayman
  • Patent number: 6228691
    Abstract: A process of producing controllable thicknesses of silicon-on-insulator (SOI) for fully-depleted double-gate applications is provided. The process comprises depositing an oxide layer on a silicon wafer, depositing a nitride layer of a controlled thickness on the oxide layer, etching the nitride layer to open a first trench of controlled thickness, opening a second trench down to the silicon substrate, growing epitaxial silicon using epitaxial lateral overgrowth (ELO) to fill the second trench and grow sideways to fill the first trench, perform planarization of ELO silicon using the nitride layer as a chemical-mechanical polishing (CMP) stop layer, and fabricating a SOI device in the first trench.
    Type: Grant
    Filed: June 30, 1999
    Date of Patent: May 8, 2001
    Assignee: Intel Corp.
    Inventor: Brian Doyle