Abstract: A method and apparatus for processing an image is described. A first area having a first value is selected. A second value for a second area surrounding the first area is determined. The first and second values are compared with a predetermined threshold. The first value is transformed according to the comparison.

Abstract: A variable width pulse generator. The pulse generator includes a pulse circuit responsive to a reset signal to provide a pulse circuit signal. A variable delay reset loop path, coupled to the pulse circuit, is responsive to the pulse circuit signal to provide the reset signal. A control signal may vary the width of a pulse generated by the circuit by varying the length of a delay associated with the reset loop path. Both a coarse control signal, such as a signal that selectively removes a logic element in the reset loop path, and a fine control signal, such as a signal that controls a tunable delay element in the reset loop path, may be used to adjust the pulse width.

Abstract: A system for compressing and decompressing a data pattern of data bits, so as to obtain a highly compressed data record. In accordance with embodiments of the invention, a group of candidate numbers is provided with each number comprising a sequence of statistically random bits. Bits of a subject data pattern are compared with bits of each candidate of the group of numbers to find a largest sequence of bits of the subject data pattern which match a sequence of bits within any one of the group of candidate numbers. Stored are all of: the data pattern except the matched bits, information designating the candidate number providing a largest matching sequence of bits, locations of the matched bits in the subject data pattern and in the candidate number, and a number encoding a number of the matched bits.

Abstract: A method and apparatus to compensate for skew in a processor clock signal. A first clock signal at a first location in the processor is compared with a reference clock signal. The first clock signal is corrected based on the results of this comparison with the reference clock signal. The clock signal may be corrected by using a programmable delay compensator. A second clock signal at a second location in the processor may be compared with the corrected first clock signal and the second clock signal may be corrected based on the results of the comparison. The compensators may be permanently programmed as required using fuses associated with compensator control bits.

Abstract: A system including a first graphics controller and an expansion slot for coupling a second graphics controller. The first graphics controller generates first graphic symbols based on data stored in the system memory in synchronism with clock signals received from a clock circuit. Similarly, the second graphics controller generates second graphic symbols based on data stored in the system memory in synchronism with clock signals received from the clock circuit. When the second graphics controller is not coupled to the expansion slot, the processor provides a graphics select signal. A clock steering circuit responds to the graphics select signal by applying the clock signals to the first graphics controller, while blocking the clock signals to the expansion slot. In the absence of the graphics select signal, the clock steering circuit applies the clock signals to the expansion slot for application to the second graphics controller, while blocking the clock signals to the first graphics controller.

Abstract: An audio coding system encodes and decodes audio signals as a plurality of independent layers of coded audio data. A basic representation of the original audio signal may be reconstructed from decoding of a single layer of coded audio data. However, a more complete representation of the original audio signal is reconstructed by decoding additional layers of coded audio data. The coding system finds application with decoding systems of varying processing power, and in transmission systems having communication channels that are characterized by intermittent transmission errors and/or variable capacity. At an encoding system, an audio signal is broken into a plurality of frequency bands which are filtered, down sampled and independently coded. A decoding system inverts the coding process applied at the encoding system for whatever number of layers that is determined will be decoded.

Abstract: A fault resilient circuit, having a ring counter, that boots a multi-device system, such as multi-processor computer system. A timer accepts start timer and system operational signals and produces a system fail signal. A ring counter accepts the system fail signal, and the ring counter produces a plurality of device control signals. With such an arrangement, when enabling all of the devices substantially simultaneously does not produce a working system, the boot circuit can for, example, enable all but one of the devices and determine if the system operates correctly with all but one of the devices enabled. If the system does not operate correctly with all but one of the devices enabled, a single device in the system can be enabled and it is determined if the system operates correctly with a single device enabled.

Abstract: An architecture for the isochronous transfer of information within a computer system in which a first isochronous stream of information is transferred, and asynchronous information is transferred independently from the transfer of the first stream. A translation is performed between the first stream and a second isochronous stream of information, and the second stream transfers information at a rate substantially the same as the rate at which the first stream transfers information. The second stream and the asynchronous information are concurrently transferred. In another embodiment of the present invention, a first isochronous stream of information is transferred, and the first stream is divided into a plurality of first service periods. Each first service period has a first duration and contains a first amount of information. A second isochronous stream of information is transferred independently from the transfer of the first stream.

Abstract: A computer processor includes a multiplexer having a first input, a second input, a third input, and an output. The processor further includes a scheduler coupled to the multiplexer first input, an execution unit coupled to the multiplexer output, and a replay system that has an input coupled to the multiplexer output. The replay system includes a first checker coupled to the replay system input and the second multiplexer input, and a second checker coupled to the first checker and the third multiplexer input.

Abstract: A method of monitoring logical connections in a computer network is described. All packets exchanged via the network are intercepted and analyzed. Upon receipt of a packet, a connection management engine determines whether packet is part of an existing logical connection. If it is not, a new record is created and stored in a connection record database. Otherwise, the existing record for the logical connection in the connection record database is updated.Also described is a method of monitoring file transfers in a computer network. File transfers are monitored using an file transfer record database, which allows each packet of the file transfer to be placed in proper context. Upon interception of a packet, an application management engine (AME) first determines whether the packet is part of a file transfer. If it is not, the AME ignores the packet.

Abstract: A memory device for a digital video system, capable of receiving video data in a packed format and transmitting that video data in a planar format. In other operating modes, the memory device receives video data in various packed formats and transmits that video data in a packed format. The memory device is suitable for a flexible digital video system in which video data may either be displayed in real time as it is generated (using packed format data) or compressed for storage and future display (using planar format data).

Abstract: A multi-layer lead frame is provided with a lead frame body made of a metal strip and having a plurality of inner leads including respective tips which define an opening. A power supply metal plane is adhered to the inner leads and a ground metal plane is adhered to the power supply metal plane by insulative adhesive layers. These metal planes are provided with first wire bonding areas and through holes in the vicinity thereof. A semiconductor device comprises such a multi-layer lead frame, a semiconductor chip mounted on a stage thereof, bonding-wires electrically connecting the chip to the areas, and a resin integrally molding the multi-layer lead frame, the chip, and the bonding-wires in such a manner that the through holes are filled with the resin.

Abstract: A multi-layer lead frame for a semiconductor device comprises a lead frame body made of a metal strip having a first opening and a plurality of inner leads having respective innertips which define the opening. A metal plane independent from the lead frame body and adhered to the inner leads by an insulation adhesive film, has an inner periphery defining a second opening corresponding to the first opening. The inner periphery of the insulation film protrudes slightly from the inner tips of the inner leads.

Abstract: A process for manufacturing a multi-layer lead frame for a semiconductor device comprises two metal plains being adhered to each other via an insulation piece. An insulation strip is punched to cut the insulation piece, which is preliminary adhered to a metal strip. The metal strip is then punched to cut and remove the metal plane, which is then laminated and heat-pressed to another metal strip. After completely adhered, the other metal strip is punched to remove a multi-layer lead frame.