Abstract: Two primitives may be merged by interpolating vertex attributes at coarse pixel centers. Input attributes are computed as a coverage weighted average of the interpolated vertex attributes. Then coarse pixel shading is performed using the merged primitives.

Abstract: In an example, an apparatus comprises a plurality of processing unit cores, a plurality of cache memory modules associated with the plurality of processing unit cores, and a machine learning model communicatively coupled to the plurality of processing unit cores, wherein the plurality of cache memory modules share cache coherency data with the machine learning model. Other embodiments are also disclosed and claimed.

Abstract: A device with support for blockchain-based boot tracking comprises at least one processor, non-volatile storage responsive to the processor, and at least one boot module in the non-volatile storage. The boot module, when executed by the processor, enables the device to generate a measurement of the boot module, generate an internal ledger transaction based on the measurement of the boot module, and send the internal ledger transaction to a remote device. In addition, the boot module enables the device to (a) receive an external ledger transaction from the remote device, wherein the external ledger transaction is based on a measurement for a boot module of the remote device; (b) in response to receiving the external ledger transaction, verify the external ledger transaction; and (c) in response to verifying the external ledger transaction, add the external ledger transaction to a boot audit blockchain. Other embodiments are described and claimed.

Abstract: Methods and apparatus relating to Multi-Sample Anti-Aliasing (MSAA) memory bandwidth reduction for sparse sample per pixel utilization are described. In an embodiment, Multi-Sample Anti-Aliasing (MSAA) logic generates render subspan plane information based on data stored in a cacheline. One or more read operations to memory are suppressed based on a determination that the cacheline is in a clear state. Other embodiments are also disclosed and claimed.

Abstract: A first threshold temperature is maintained for operating a solid state drive (SSD) in a first mode. A second threshold temperature is maintained for operating the SSD in a second mode in which read and write operations are performed at a higher rate than in the first mode, wherein the second threshold temperature is higher than the first threshold temperature. The SSD is switched from the first mode to the second mode, in response to an operating temperature of the SSD exceeding the first threshold temperature.

Abstract: The graphics pipeline produces real time utilization data for each of a plurality of functional units making up an overall graphics processor or graphics system on a chip. This information may be used for fine grain management of power consumption and performance at the functional unit level as opposed the overall device level. As a result, the graphics functional units may be managed dynamically based on real time hardware metrics to improve performance and reduce power consumption. The technique may be implemented in a software module in one embodiment.

Abstract: In one embodiment, the present invention includes a method for providing power state change information from a plurality of cores of a processor to a predictor at a periodic interval and generating a prediction to indicate a predicted operation level of the cores during a next operating period. Other embodiments are described and claimed.

Abstract: Disclosed herein are integrated circuit (IC) packages with temperature sensor traces, and related systems, devices, and methods. In some embodiments, an IC package may include a package substrate and an IC die disposed on the package substrate, wherein the package substrate includes a temperature sensor trace, and an electrical resistance of the temperature sensor trace is representative of an equivalent temperature of the temperature sensor trace.

Abstract: Technologies of managing power during an activation cycle of a processor core or other compute domain include determining new operation limits for active processor cores or other compute domains during an activation cycle of a hibernating processor core or other hibernating compute domain to reduce the likelihood of a power surge during the activation of the hibernating processor core or other compute domain. The active processor cores or other compute domain are monitored until their operating points are at or below the new operating limits. Thereafter, the hibernating processor core or other hibernating compute domain is activated.

Abstract: Transistors suitable for high voltage and high frequency operation are disclosed. A nanowire is disposed vertically or horizontally on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first semiconductor material, a source region electrically coupled with a first end of the channel region, a drain region electrically coupled with a second end of the channel region, and an extrinsic drain region disposed between the channel region and drain region. The extrinsic drain region has a wider bandgap than that of the first semiconductor. A gate stack including a gate conductor and a gate insulator coaxially wraps completely around the channel region, drain and source contacts similarly coaxially wrap completely around the drain and source regions.

Abstract: This disclosure describes systems, methods, and computer-readable media related to cross indication of queue size in a reverse direction protocol. In some embodiments, a reverse direction (RD) grantor may transmit a frame to an RD responder. The RD responder may identify data to be transmitted to the RD grantor based on the received frame. The RD responder may generate a frame that may comprise a plurality of sub-frames. The RD responder may set a sub-field in each of the sub-frames indicating whether there is data to transmit. The RD responder may also set a second sub-field that may indicate a priority or traffic stream associated with the data to be transmitted. The RD responder may transmit the frame (and associated sub-frames) to the RD grantor.

Abstract: Methods, apparatuses and storage medium associated with navigation service are disclosed. In various embodiments, a method may include collecting, by a client mobile device, ambient barometric pressure information at a current location of the client mobile device. The method may further include providing, by the mobile device, contemporaneous navigation assistance to a user of the mobile device or for a user of the mobile device, assisted by a remote navigation assistance service. Assistance by the remote navigation service is associated with determining the current elevation level, based at least in part on ambient barometric pressure information collected by the client mobile device and by one or more crowdsourced mobile devices at the current location. Other embodiments may be disclosed or claimed.

Abstract: Embodiments of methods to communicate a timestamp to a storage system are generally described herein. Other embodiments may be described and claimed.

Abstract: Some demonstrative embodiments include apparatuses, devices, systems and methods of communicating a wide-bandwidth data frame. For example, an apparatus may include a controller to generate at least one wide-bandwidth data frame to be transmitted over a wide-bandwidth millimeter-Wave (mmWave) channel, the wide-bandwidth mmWave channel including a plurality of mmWave channels; and a transmitter to transmit a plurality of reservation frames over the plurality of mmWave channels, a reservation frame of the plurality of reservation frames including a duration value corresponding to a duration of the wide-bandwidth data frame and a wide-bandwidth indication to indicate that the wide-bandwidth data frames are to be transmitted over the wide-bandwidth mmWave channel, the transmitter to transmit the at least one wide-bandwidth data frame over the wide-bandwidth mmWave channel.

Abstract: Techniques are disclosed for processing a video stream to reduce platform power by employing a stepped and distributed pipeline process, wherein CPU-intensive processing is selectively performed. The techniques are particularly well-suited for hand-based navigational gesture processing. In one example case, for instance, the techniques are implemented in a computer system wherein initial threshold detection (image disturbance) and optionally user presence (hand image) processing components are proximate to or within the system's camera, and the camera is located in or proximate to the system's primary display. In some cases, image processing and communication of pixel information between various processing stages which lies outside a markered region is suppressed. In some embodiments, the markered region is aligned with, a mouse pad or designated desk area or a user input device such as a keyboard. Pixels evaluated by the system can be limited to a subset of the markered region.

Abstract: Methods, apparatus, and system to analyze a memory integrity violation and determine whether its cause was hardware or software based.

Abstract: A control surface tracks an individual cacheline in the original surface for frequent data values. If so, control surface bits are set. When reading a cacheline from memory, first the control surface bits are read. If they happen to be set, then the original memory read is skipped altogether and instead the bits from the control surface provide the value for the entire cacheline.

Abstract: Aspects of the embodiments are directed to systems, methods, and devices for generating a design of experiments (DOE) matrix, the DOE matrix comprising a set of possible combinations of values for a plurality of electrical parameters; iteratively applying each combination of values for the plurality of electrical parameters to one or more memory pins; determining a margin response for each combination of values; generating a prediction function based on a correlation of the margin response and each combination of values; and optimizing the plurality of electrical parameters based on the prediction function.

Abstract: Vertical non-planar semiconductor devices for system-on-chip (SoC) applications and methods of fabricating vertical non-planar semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a substrate, the semiconductor fin having a recessed portion and an uppermost portion. A source region is disposed in the recessed portion of the semiconductor fin. A drain region is disposed in the uppermost portion of the semiconductor fin. A gate electrode is disposed over the uppermost portion of the semiconductor fin, between the source and drain regions.

Abstract: Disclosed are EMI shielded packages, electronic device packages, and related methods. EMI shielded packages are formed by applying an insulating material to a first side of a substrate strip, separating the substrate strip into segments, adhering the insulating material of the segments to a solid conductor, applying a conductive paste around lateral sides of the segments, curing the conductive paste, and cutting through the conductive paste and the solid conductor to form the EMI packages. An electronic device package includes a substrate including electronic circuitry, an EMI shield, and an insulating material insulating the substrate from the EMI shield. The EMI shield includes a solid conductor adhered to the insulating material, and a cured conductive paste at least partially surrounding a lateral edge of the substrate. The cured conductive paste electrically connects the solid conductor to a conductive terminal in a lateral side of the substrate.