Abstract: The disclosed embodiments generally relate to detecting malware through detection of micro-architectural changes (morphing events) when executing a code at a hardware level (e.g., CPU). An exemplary embodiment relates to a computer system having: a memory circuitry comprising an executable code; a central processing unit (CPU) in communication with the memory circuitry and configured to execute the code; a performance monitoring unit (PMU) associated with the CPU, the PMU configured to detect and count one or more morphing events associated with execution of the code and to determine if the counted number of morphine events exceed a threshold value; and a co-processor configured to initiate a memory scan of the memory circuitry to identify a malware in the code.

Abstract: An embodiment of a semiconductor package apparatus may include technology to identify a nested loop in a set of executable instructions, and determine at runtime if the nested loop is a candidate for cache blocking. Other embodiments are disclosed and claimed.

Abstract: Systems, apparatuses and methods may provide for technology that identifies a thread and selects a core from a plurality of processor cores in response to the selected core being available while satisfying a least used condition with respect to the plurality of processor cores. The technology may also schedule the thread to be executed on the selected core.

Abstract: Systems, methods, and devices can include ports comprising hardware to support the multilane link, wherein the multi-lane link comprises a first set of bundled lanes configured in a first direction and a second set of bundled lanes configured in a second direction, the second direction is opposite to the first direction, the first set of bundled lanes comprises an equal number of lanes as the second set of bundled lanes. An input/output (I/O) bridge logic implemented at least partially in hardware can receive across the multilane link an cache invalidation request received on a port compliant with an I/O protocol. A memory controller logic implemented at least partially in hardware can invalidate a cache line based on receiving the cache invalidation request on the I/O protocol. The memory controller can transmit across the multilane link a memory invalidation response message on a port compliant with a device-attached memory access protocol.

Abstract: Systems, apparatuses and methods may provide for technology that generates, by a first neural network, an initial set of model weights based on input data and iteratively generates, by a second neural network, an updated set of model weights based on residual data associated with the initial set of model weights and the input data. Additionally, the technology may output a geometric model of the input data based on the updated set of model weights. In one example, the first neural network and the second neural network reduce the dependence of the geometric model on the number of data points in the input data.

Abstract: Systems and methods of generating a synchronized media content presentation using a plurality of media output systems communicably coupled to a respective plurality of network connected platforms are provided. A first network connected platform receives an IEEE 802.1AS master timing signal generated by “Grand Master” timing circuitry disposed in a second network connected platform. IEEE 802.1AS application service circuitry disposed in the first network connected platform determines an offset between a local timing signal and the receive master timing signal. Talker circuitry disposed in the first network connected platform synchronizes a media content presentation to the master timing signal and communicates a media/master timing signal synchronization signal to each of the network connected platforms. The media/master timing signal synchronization signal includes data representative of a media start location and a media start time referenced to the master timing signal.

Abstract: Devices for computing the sum of multiple Vector-Vector Dot-Products (VVDP) or multiple partial sums of VVDP can include a resistive memory array and a reduction circuit. The reduction circuit can be configured to determine a sum of a selected one or more of a plurality of bit lines of the resistive memory array. A VVDP reduction can be determined from the sum of the selected one or more of the plurality of bit lines.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a first gate and an adjacent second gate above the quantum well stack; and a gate wall between the first gate and the second gate, wherein the gate wall includes a spacer and a capping material, the spacer has a top and a bottom, the bottom of the spacer is between the top of the spacer and the quantum well stack, and the capping material is proximate to the top of the spacer.

Abstract: Technology for a memory controller is described. The memory controller can receive a request from a data consumer node in a data center for training data. The training data indicated in the request can correspond to a model identifier (ID) of a model that runs on the data consumer node. The memory controller can identify a data provider node in the data center that stores the training data that is requested by the data consumer node. The data provider node can be identified using a tracking table that is maintained at the memory controller. The memory controller can send an instruction to the data provider node that instructs the data provider node to send the training data to the data consumer node to enable training of the model that runs on the data consumer node.

Abstract: Technologies are provided in embodiments including a memory element to store a payload indicating an action to be performed associated with a remote action request (RAR) and a remote action handler circuit to identify the action to be performed, where the action includes invalidating one or more entries of a translation lookaside buffer (TLB), determine that the logical processor entered an enclave mode during a prior epoch, perform one or more condition checks on control and state pages of the enclave mode, and based on results of the one or more condition checks, adjust one or more variables associated with the logical processor to simulate the logical processor re-entering the enclave mode. Specific embodiments include the remote action handler circuit to invalidate an entry of the TLB based, at least in part, on the results of the one or more condition checks.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a layer of gate dielectric above the quantum well stack; a first gate metal and a second gate metal above the layer of gate dielectric; and a gate wall between the first gate metal and the second gate metal, wherein the gate wall is above the layer of gate dielectric, and the gate wall includes a first dielectric material and a second dielectric material different from the first dielectric material.

Abstract: A shielded SODIMM system for reducing RF emissions of a SODIMM connector is disclosed herein. SODIMM connector RFI presently interferes with connectivity and is also an obstacle for higher speed memory applications. The shielded SODIMM system includes a SODIMM connector that is at least partially housed by a SODIMM connector shield, to partially and/or substantially reduce or block RF emissions from the SODIMM connector. The SODIMM connector shield is at least partially conductive and is coupled to landing pads on a surface of a motherboard printed circuit board (“PCB”). The landing pads of the motherboard PCB that are coupled to the SODIMM connector shield are coupled to ground, which grounds the SODIMM connector shield. Grounding the SODIMM connector shield that at least partially houses the SODIMM connector reduces RF emissions from the SODIMM connector during information transfer operations.

Abstract: An embodiment of a semiconductor package apparatus may include technology to generate a first output from a physically unclonable function (PUF) based on a challenge, modify the challenge based on the first output, and generate a response based on the modified challenge. Some embodiments may additionally or alternatively include technology to change a read sequence of the PUF based on an output of the PUF. Some embodiments may additionally or alternatively include technology to vary a latency of a linear feedback shift register based on an output from the PUF. Other embodiments are disclosed and claimed.

Abstract: Electronic device heat transfer technology is disclosed. In an example, an electronic device package can include a substrate. The electronic device package can also include a heat transfer component. The electronic device package can further include a heat-generating electronic component coupled to the substrate between the substrate and the heat transfer component. The electronic device package can also include a viscous thermal interface material (TIM) providing a heat transfer pathway between the electronic component and the heat transfer component. In addition, the electronic device package can include a barrier about at least a portion of a periphery of the viscous TIM to maintain the viscous TIM within a confined location in proximity to the electronic component. The TIM is uninterrupted by the barrier within the periphery.

Abstract: An embodiment of a semiconductor package apparatus may include technology to identify a field of a data structure as a candidate for a size reduction, perform a runtime analysis on the field, and reduce the size of the field based on the runtime analysis. Other embodiments are disclosed and claimed.

Abstract: In one aspect, an apparatus for detecting fatigue comprises a dry-contact electroencephalogram (EEG) electrode to measure EEG data operably coupled to at least one processor. The at least one processor is to: calculate a frequency domain representation of the EEG data, detect spectral features indicative of fatigue based on the frequency domain representation; and determine whether the brain is fatigued based on the detection. In another aspect, a method for detecting fatigue comprises receiving EEG data from dry-contact EEG electrode, calculating a frequency domain representation of the EEG data, detecting spectral features indicative of fatigue based on the frequency domain representation; and determining whether the brain is fatigued based on the detection.

Abstract: An integrated circuit package may include one or more integrated circuit dies and reconfigurable constrained vapor bubble (CVB) heat pipe structures formed on the integrated circuit dies. The reconfigurable CVB heat pipe structures may be adjusted using micro-electro-mechanical systems (MEMS) switches. By turning on a MEMS switch, the corresponding heat pipe structure will exhibit a first heat transfer efficiency. By turning off a MEMS switch, the corresponding heat pipe structure will exhibit a second heat transfer efficiency that is less than the first heat transfer efficiency. The reconfigurable CVB heat pipe structures may be statically programmed and/or dynamically adjusted as hot spot locations within the integrated circuit package migrate over time.

Abstract: Embodiments of the present disclosure describe two approaches to providing flux bias line structures for superconducting qubit devices. The first approach, applicable to flux bias line structures that include at least one portion that terminates with a ground connection, resides in terminating such a portion with a ground connection that is electrically isolated from the common ground plane of a quantum circuit assembly. The second approach resides in providing a SQUID loop of a superconducting qubit device and a portion of the flux bias line structure over a portion of a substrate that is elevated with respect to other portions of the substrate. These approaches may be used or alone or in combination, and may improve grounding of and reduce crosstalk caused by flux bias lines in quantum circuit assemblies.

Abstract: Technology for a display device is described. The display device can include at least one display screen operable to show at least one display panel. The display device can include a controller. The controller can receive a content frame from a content source over a transport topology. The controller can receive a presentation timestamp (PTS) associated with the content frame, where the PTS indicates an earliest time at which the content frame is to be displayed at the display device. The controller can provide the content frame for display on the display panel at a subsequent panel refresh opportunity in accordance with the PTS.

Abstract: Techniques related to applying computer vision to decompressed video are discussed. Such techniques may include generating a region of interest in an individual video frame by translating spatial indicators of a first detected computer vision result from a reference video frame to the individual video frame and applying a greater threshold within the region of interest than outside of the region of interest for computer vision evaluation in the individual frame.