Abstract: Particular embodiments described herein provide for an electronic device that can be configured to help with the identification of a no-operation (NOP) sled attack identify. The system can be configured to receive an instruction, increment a value in a total instruction counter, increment a value in a branch instruction counter when the instruction is a branch instruction, increment a value in a memory instruction counter when the instruction is a memory instruction, create a ratio based on the value in the total instruction counter and the value in the branch instruction counter or the value in the memory instruction counter, and trigger an alert when the ratio satisfies a threshold. The ratio can indicate the presence of a NOP sled attack and the alert can be an interrupt that stops execution of the NOP sled.

Abstract: A mechanism is described for facilitating protection and recovery of identities in surveillance camera environments according to one embodiment. An apparatus of embodiments, as described herein, includes detection and reception logic to receive a video stream of a scene as captured by a camera, wherein the scene includes persons. The apparatus may further include recognition and application logic to recognize an abnormal activity and one or more persons associated with the abnormal activity in a video frame of the video stream. The apparatus may further include identity recovery logic to recover one or more identities of the one or more persons in response to the abnormal activity, where the one or more identities are recovered from masked data and encrypted residuals associated with the one or more persons.

Abstract: An IC, operable at a first clock phase, includes first and second IOs and a PLL. The PLL includes a control circuit, an input to receive a first clock signal, an output to output a second clock signal, and a first detector to generate a first phase difference signal from the first and second clock signals. The IC includes a second phase detector that is coupled to the PLL's output to receive the second clock signal and is coupled to the first IO to receive a third clock single from a second IC, which is operable at a second clock phase. The second detector generates a second phase difference signal from the second and third clock signals. If the PLL uses the second phase difference signal to generate the second clock signal, then the second clock signal is synchronized with the third clock signal for synchronous data transfer.

Abstract: An embodiment of a semiconductor package apparatus may include technology to test a target query for one or more similarity metrics over a range of parameters for one or more sets of sequence related information, a multi-domain sequence model, and one or more training routines, select a set of parameters based on a result of the test, and automatically configure the multi-domain sequence model to adapt to one or more of respective data sets, respective prediction tasks, and respective recommendation tasks based on the selected parameters. Other embodiments are disclosed and claimed.

Abstract: An embodiment of a semiconductor package apparatus may include technology to determine if a wake event corresponds to a zero-power state of a computer operating system, determine if a run-time state is valid to wake the operating system from the zero-power state, and wake the operating system from the zero-power state to the run-time state if the run-time state is determined to be valid. Other embodiments are disclosed and claimed.

Abstract: Methods and apparatus related to checkpointing for Solid State Drives (SSDs) that include no DRAM (Dynamic Random Access Memory) are described. In one embodiment, Non-Volatile Memory (NVM) stores an original Logical address to Physical address (L2P) table entry and a shadow L2P table entry. Allocation logic circuitry causes storage of the original L2P table entry and the shadow L2P table entry sequentially in the NVM. Data read from the shadow L2P table entry is capable to indicate a state of the original L2P table entry. Other embodiments are also disclosed and claimed.

Abstract: Techniques are disclosed for forming transistors including one or more group III-V semiconductor material nanowires using sacrificial group IV semiconductor material layers. In some cases, the transistors may include a gate-all-around (GAA) configuration. In some cases, the techniques may include forming a replacement fin stack that includes group III-V material layer (such as indium gallium arsenide, indium arsenide, or indium antimonide) formed on a group IV material buffer layer (such as silicon, germanium, or silicon germanium), such that the group IV buffer layer can be later removed using a selective etch process to leave the group III-V material for use as a nanowire in a transistor channel. In some such cases, the group III-V material layer may be grown pseudomorphically to the underlying group IV material, so as to not form misfit dislocations. The techniques may be used to form transistors including any number of nanowires.

Abstract: Methods and apparatus to improve shared memory efficiency are described. In an embodiment, a first version of a code to access one or more registers as shared local memory is compiled. A second version of the same code is also compiled to access a cache as the shared local memory. The first version of the code is executed in response to comparison of a work group size of the code with a threshold value. Other embodiments are also disclosed and claimed.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer and a barrier layer; a first gate metal above the quantum well stack, wherein the barrier layer is between the first gate metal and the quantum well layer; and a second gate metal above the quantum well stack, wherein the barrier layer is between the second gate metal and the quantum well layer, and a material structure of the second gate metal is different from a material structure of the first gate metal.

Abstract: An embodiment of a semiconductor package apparatus may include technology to embed one or more trigger operations in one or more messages related to collective operations for a neural network, and issue the one or more messages related to the collective operations to a hardware-based message scheduler in a desired order of execution. Other embodiments are disclosed and claimed.

Abstract: A transceiver circuit includes a clock management circuit that generates control signals indicating power state information for logic circuits. The clock management circuit changes the power state information indicated by the control signals based on a change in an indication of a power state that is generated by an external source and that is received in a data stream at the transceiver circuit or based on a change in an amount of data stored in an internal queue. The transceiver circuit also includes a dynamic clock control circuit that receives the control signals and that generates a clock signal that is provided to the logic circuits. The dynamic clock control circuit adjusts a frequency of the clock signal based on the control signals indicating a change in the power state information generated by the clock management circuit to adjust the power state of the logic circuits.

Abstract: Aspects of the embodiments are directed to a port comprising hardware to support the multi-lane link, the link comprising a lane that comprises a first differential signal pair and a second differential signal pair. Link configuration logic, implemented at least in part in hardware circuitry, can determine that the port comprises hardware to support one or both of receiving data on the first differential signal pair or transmitting data on the second differential signal pair, and reconfigure the first differential signal pair to receive data with the second differential signal pair or reconfigure the second differential signal pair to transmit data with the first differential signal pair; and wherein the port is to transmit data or receive data based on reconfiguration of one or both the first differential signal pair and the second differential signal pair.

Abstract: The present disclosure is directed to systems and methods for mitigating or eliminating the effectiveness of a side channel attack, such as a Spectre type attack, by limiting the ability of a user-level branch prediction inquiry to access system-level branch prediction data. The branch prediction data stored in the BTB may be apportioned into a plurality of BTB data portions. BTB control circuitry identifies the initiator of a received branch prediction inquiry. Based on the identity of the branch prediction inquiry initiator, the BTB control circuitry causes BTB look-up circuitry to selectively search one or more of the plurality of BTB data portions.

Abstract: The present disclosure is directed to systems and methods that include cache operation storage circuitry that selectively enables/disables the Cache Line Flush (CLFLUSH) operation. The cache operation storage circuitry may also selectively replace the CLFLUSH operation with one or more replacement operations that provide similar functionality but beneficially and advantageously prevent an attacker from placing processor cache circuitry in a known state during a timing-based, side channel attack such as Spectre or Meltdown. The cache operation storage circuitry includes model specific registers (MSRs) that contain information used to determine whether to enable/disable CLFLUSH functionality. The cache operation storage circuitry may include model specific registers (MSRs) that contain information used to select appropriate replacement operations such as Cache Line Demote (CLDEMOTE) and/or Cache Line Write Back (CLWB) to selectively replace CLFLUSH operations.

Abstract: Techniques related to video encoding that provide for a decoupled prediction and coding structure for improved performance are discussed. Such techniques include determining final partitioning decisions for blocks of a picture by evaluating intra modes for candidate partitions by comparing the candidate partitions to intra predicted partitions generated using only original pixel samples and evaluating inter modes for the candidate partitions by comparing the candidate partitions to search partitions including original pixel samples and encoding using the final partitioning decision.

Abstract: Particular embodiments described herein provide for an electronic device that can be configured to receive a request for data, wherein the request is received on a system that regularly stores data in a cache and provide the requested data without causing the data or an address of the data to be cached or for changes to the cache to occur. In an example, the requested data is already in a level 1 cache, level 2 cache, or last level cache and the cache does not change its state. Also, a snoop request can be broadcasted to acquire the requested data and the snoop request is a read request and not a request for ownership of the data. In addition, changes to a translation lookaside buffer when the data was obtained using a linear to physical address translation is prevented.

Abstract: Methods and apparatus relating to a physics-based approach for attack detection and/or localization in closed-loop controls for autonomous vehicles are described. In an embodiment, multiple state estimators are used to compute a set of residuals to detect, classify, and/or localize attacks. This allows for determination of an attacker's location and the kind of attack being perpetrated. Other embodiments are also disclosed and claimed.

Abstract: A method and apparatus for self-adjusting networks including internet-of-things (loT) devices is provided. An exemplary system includes a source discovery system configured to identify if a source sending a message is in a database, and, if not, add the source to the database and rank the source by link metrics of messages received from the source. A sink discovery system is configured to identify if a sink receiving a message is in a database, and, if not, add the sink to the database. The sink discovery system is configured to rank the sink by link metrics of messages responded to by the sink. A dynamic mapping system is configured to create a dynamic map of communications between a source and a sink, and implement a self-healing subsystem to restore a loss of communications between a source and a sink.

Abstract: Techniques and mechanisms for mitigating the effect of signal noise on communication via an interconnect. In an embodiment, a substrate includes an interconnect and a conductor which has a hole formed therein. Portions of the interconnect variously extend over a side of the conductor, wherein another recess portion of the interconnect extends from a plane which includes the side, and further extends at least partially into the hole. The configuration of the recess portion extending within the hole may contribute to an impedance which dampens a transmitter slew rate of the communication. In an embodiment, a total distance along a path formed by the interconnect is equal to or less than 5.5 inches.

Abstract: Systems, devices, and techniques related to selecting a key frame for burst image processing are discussed. Such techniques may include generating key frame scores for at least some frames of a multi-frame burst image capture such that the key frame scores include a combination of an image quality component, a shutter lag component, and a burst image processing latency component and selecting a frame having a maximum key frame score as the key frame.