Abstract: Disclosed herein are inorganic dies with organic interconnect layers and related structures, devices, and methods. In some embodiments, an integrated circuit (IC) structure may include an inorganic die and one or more organic interconnect layers on the inorganic die, wherein the organic interconnect layers include an organic dielectric.

Abstract: An apparatus to facilitate page translations is disclosed. The apparatus comprises a frame buffer to a plurality of pages of data, a plurality of display page tables to store virtual address to physical address translations to the pages of data in the frame buffer and a page table having a plurality of page table entries (PTEs), wherein each PTE maps to one of the plurality of display page tables.

Abstract: This disclosure describes systems, methods, and devices related to using protected beacon frames in wireless communications. A device may determine a beacon management element of a beacon frame body and may determine an integrity group key identifier of the beacon management element, wherein the integrity group key identifier is associated with a basic service set (BSS). The device may determine, based on the integrity group key identifier, a management integrity check (MIC) field of the beacon management element. The device may generate a beacon frame including the beacon frame body. The device may send the beacon frame.

Abstract: A variable delay circuit includes first pull-up and first pull-down current paths and second pull-up and second pull-down current paths. The variable delay circuit generates first delays in an output signal relative to an input signal in response to the first pull-up and first pull-down current paths being enabled by a first control signal. The variable delay circuit generates second delays in the output signal relative to the input signal that are different than the first delays in response to the second pull-up and second pull-down current paths being enabled by a second control signal.

Abstract: Various systems and methods for obtaining vendor information using mobile internet devices are described herein. An inquiry for a product or service is received from a user. A location for the receipt of the product or service is received. Vendor information of a vendor of the product or service proximate to the location is determined, with the vendor information including a price for the product or service, and a wait time to receive the product or service. The vendor information is then transmitted to the user.

Abstract: Embodiments are generally directed to automatic adjustment of head mounted display straps. An embodiment of a head mounted display apparatus includes a display unit; a strap harness including one or more straps; one or more pressure sensors; a microcontroller; and one or more automatic adjustment mechanisms for the one or more straps, wherein the microcontroller is to adjust the one or more straps by controlling operation of the one or more automatic adjustment mechanisms based at least in part on sensor data from the one or more pressure sensors.

Abstract: Systems, apparatuses and methods may provide for establishing a hardware-based chain of trust in a computing system and extending the hardware-based chain of trust to a container manager and a containerized application on the computing system. Additionally, the containerized application may be checked for its trust and security while it is launched, via the container manager, on the computing system. In one example, extending the hardware-based chain of trust includes conducting a pre-boot measurement of the container manager, a root of trust measurement agent, and one or more packages associated with the containerized application, and verifying the pre-boot measurement of the platform/host and the application itself prior to the containerized application being launched.

Abstract: Various embodiments are generally directed to techniques for multi-domain memory encryption, such as with a plurality of cryptographically isolated domains, for instance. Some embodiments are particularly directed to a multi-domain encryption system that provides one or more of memory encryption, integrity, and replay protection services to a plurality of cryptographic domains. In one embodiment, for example, an apparatus may comprise a memory and logic for an encryption engine, at least a portion of the logic implemented in circuitry coupled to the memory. In various embodiments, the logic may receive a memory operation request associated with a data line of a set of data lines stored in a protected memory separate from the memory.

Abstract: Various systems and methods for managing graphics subsystems are described herein. A system for managing graphics subsystems of a compute device includes a display controller operable to: receive an indication that a first display of the compute device has been activated; enable a power management feature in a display controller, the power management feature to reduce power consumption of the display controller and associated components, and the power management feature to reduce graphics memory bandwidth usage; receive an indication that a second display has been activated with the first display; and maintain the power management feature for at least the first display.

Abstract: Technologies for providing certified telemetry data indicative of resource utilizations include a device with circuitry configured to obtain telemetry data indicative of a utilization of one or more device resources over a time period. The circuitry is additionally configured to sign the obtained telemetry data with a private key associated with the present device. Further, the circuitry is configured to send the signed telemetry data to a telemetry service for analysis.

Abstract: An embedded multi-die interconnect bridge apparatus and method includes photolithographically formed interconnects coupled to laser-drilled interconnects. Several structures in the embedded multi-die interconnect bridge apparatus exhibit characteristic planarization during fabrication and assembly.

Abstract: Techniques are disclosed for co-integrating thin-film bulk acoustic resonator (TFBAR, also called FBAR) devices and III-N semiconductor transistor devices. In accordance with some embodiments, a given TFBAR device may include a superlattice structure comprising alternating layers of an epitaxial piezoelectric material, such as aluminum nitride (AlN), and any one, or combination, of other III-N semiconductor materials. For instance, aluminum indium nitride (AlxIn1-xN), aluminum gallium nitride (AlxGa1-xN), or aluminum indium gallium nitride (AlxInyGa1-x-yN) may be interleaved with the AlN, and the particular compositional ratios thereof may be adjusted to customize resonator performance. In accordance with some embodiments, the superlattice layers may be formed via an epitaxial deposition process, allowing for precise control over film thicknesses, in some cases in the range of a few nanometers.

Abstract: Techniques are provided for training and operation of a topic-guided image captioning system. A methodology implementing the techniques according to an embodiment includes generating image feature vectors, for an image to be captioned, based on application of a convolutional neural network (CNN) to the image. The method further includes generating the caption based on application of a recurrent neural network (RNN) to the image feature vectors. The RNN is configured as a long short-term memory (LSTM) RNN. The method further includes training the LSTM RNN with training images and associated training captions. The training is based on a combination of: feature vectors of the training image; feature vectors of the associated training caption; and a multimodal compact bilinear (MCB) pooling of the training caption feature vectors and an estimated topic of the training image. The estimated topic is generated by an application of the CNN to the training image.

Abstract: Identifying a local coordinate system is described for gesture recognition. In one example, a method includes receiving a gesture from a user across a horizontal axis at a depth camera, determining a horizontal vector for the user based on the received user gesture, determining a vertical vector; and determining a rotation matrix to convert positions of user gestures received by the camera to a frame of reference of the user.

Abstract: Techniques are provided for optimizing the operations of an ICN, particularly for an ICN with clustered nodes. A cluster head node may function as an orchestrator and a coordinator for efficient caching, routing, and computing and for co-existence of ICN and IP nodes in the network. A content store of an ICN router may include an indication of the time after which data expires and the new data is to be swapped in place of the expired data after that point in time. Digital rights management (DRM) enforcement is provided by managing access to a DRM engine in at least one of the ICN nodes in a cluster. Congestion control is provided by minimizing the number of ICN scoped interest requests and thereby minimizing the potentially high volume of data responses. These techniques optimize interest packet forwarding and processing through collaboration with neighboring ICN nodes.

Abstract: Methods and apparatus to adaptively manage data collection devices in distributed computing systems are disclosed. Example disclosed methods involve instructing a first data collection device to operate according to a first rule. The example first rule specifies a first operating mode and defining a first event of interest. Example disclosed methods also involve obtaining first data from the first data collection device while operating according to the first rule. Example disclosed methods also involve, in response to determining that the first event of interest has occurred based on the first data, providing a second rule based on the first data to the first data collection device, and providing a third rule to a second data collection device. The example second rule specifies a second operating mode and defines a second event of interest, and the examples third rule specifies a third operating mode.

Abstract: Embodiments described herein provided for an instruction and associated logic to enable GPGPU program code to access special purpose hardware logic to accelerate dot product operations. One embodiment provides for a graphics processing unit comprising a fetch unit to fetch an instruction for execution and a decode unit to decode the instruction into a decoded instruction. The decoded instruction is a matrix instruction to cause the graphics processing unit to perform a parallel dot product operation. The GPGPU also includes a systolic dot product unit to execute the decoded instruction across one or more SIMD lanes using multiple systolic layers, wherein to execute the decoded instruction, a dot product computed at a first systolic layer is to be output to a second systolic layer, wherein each systolic layer includes one or more sets of interconnected multipliers and adders, each set of multipliers and adders to generate a dot product.

Abstract: In a computer system, a multilevel memory includes a near memory device and a far memory device, which are byte addressable. The multilevel memory includes a controller that receives a data request including original tag information. The controller includes routing hardware to selectively provide alternate tag information for the data request to cause a cache hit or a cache miss to selectively direct the request to the near memory device or to the far memory device, respectively. The controller can include selection circuitry to select between the original tag information and the alternate tag information to control where the data request is sent.

Abstract: An Analog-to-Digital Converter, ADC, system is provided. The ADC system comprises a plurality of ADC circuits and a first input for receiving a transmit signal of a transceiver. One ADC circuit of the plurality of ADC circuits is coupled to the first input and configured to provide first digital data based on the transmit signal. The ADC system further comprises a second input for receiving a receive signal of the transceiver. The other ADC circuits of the plurality of ADC circuits are coupled to the second input, wherein the other ADC circuits of the plurality of ADC circuits are time-interleaved and configured to provide second digital data based on the receive signal. Additionally, the ADC system comprises a first output configured to output digital feedback data based on the first digital data, and a second output configured to output digital receive data based on the second digital data.

Abstract: A mesh interconnect interface includes a dielectric slice; first micro-bumps aligned along a longitudinal axis and positioned closest to a driver bank, which is to be coupled to a first mesh stop of a first chiplet; second micro-bumps similarly aligned and positioned farthest from the first driver bank; third micro-bumps similarly aligned and positioned closest to a second driver bank, which is to be coupled to a second mesh stop of a second chiplet; fourth micro-bumps similarly aligned and positioned farthest from the second driver bank, wherein the longitudinal axis is orthogonal to a gap between the chiplets. The groups of micro-bumps are disposed on the slice. A first group of wires are embedded in the slice to couple the first and second micro-bumps. A second group of wires are interleaved with the first group of wires and embedded in the slice to couple the second and third micro-bumps.