Abstract: Embodiments include an autonomous core perimeter, configured to save the state of a core of a multi-core processor prior to the processor package being placed into a low-power state. The autonomous core perimeter of each core is configured to save an image of a microcontroller firmware to an external store if it has not been previously saved by another core, along with the unique working state information of that core's microcontroller. Upon restore, the single microcontroller firmware image is retrieved from the external store and pushed to each core along with each core's unique working state.

Abstract: Disclosed herein are techniques to provide forward error correction for a high-speed interconnect symbol stream, such as, DisplayPort. The symbol stream may be split into FEC blocks and parity bits generated for each of the FEC blocks. The parity bits may be interleaved, encoded, and transmitted over an interconnect along with the symbol stream to provide forward error correction for the symbol stream.

Abstract: Examples are disclosed for configuring a solid state drive (SSD) to operate in a storage mode or a memory mode. In some examples, one or more configuration commands may be received at a controller for an SSD having one or more non-volatile memory arrays. The SSD may be configured to operate in at least one of a storage mode, a memory mode or a combination of the storage mode or the memory mode based on the one or more configuration commands. Other examples are described and claimed.

Abstract: Technologies for link capability estimation are disclosed. A compute device may determine a maximum radio bitrate for a certain connection, such as an LTE connection to a specific cell antenna. The compute device may also determine a maximum downlink bitrate for that connection, and store both the maximum radio bitrate and the maximum downlink bitrate in a database on the compute device. At a later time, an application of the compute device may want to know an estimate of the current maximum downlink bitrate, such as for the purpose of selecting a bitrate in streaming a video. The compute device can determine the current maximum radio bitrate, and look for similar entries in the database. Based on entries in the database, a link capability estimation can be determined and provided to the application.

Abstract: In an embodiment, the present invention is directed to a processor including a decode logic to receive a multi-dimensional loop counter update instruction and to decode the multi-dimensional loop counter update instruction into at least one decoded instruction, and an execution logic to execute the at least one decoded instruction to update at least one loop counter value of a first operand associated with the multi-dimensional loop counter update instruction by a first amount. Methods to collapse loops using such instructions are also disclosed. Other embodiments are described and claimed.

Abstract: An apparatus to facilitate matrix processing is disclosed. The apparatus comprises a matrix accelerator to receive input matrix data, transform the input matrix data into a plurality of sub-blocks, examine a first block of the sub-blocks to determine whether the first block comprises sparse data, select a first tile size upon a determination that the first block comprises sparse data and generate output matrix data based on the first tile size.

Abstract: Two liquid cooling mechanisms are provided for cooling integrated circuit components immersed in an open bath immersion tank. In the first mechanism, heat generated by high-thermal design power (TDP) components is absorbed by a working fluid passing through cold plates coupled to the high-TDP components. The cold plates are part of direct liquid cooling loops attached to supply and return manifolds fluidly connected to a cooling distribution unit. In the second mechanism, integrated circuit components not coupled to any of the direct liquid cooling loops dissipate heat directly to the immersion fluid. In some embodiments, the tank is a closed bath immersion tank and heat captured by the working fluid is reclaimed and converted to electricity. Working fluid flow rate can be adjusted based on integrated circuit component power consumption levels to achieve a desired working fluid temperature as it enters an energy reclamation unit.

Abstract: In one embodiment, an apparatus includes a port comprising circuitry to couple the apparatus to one or more devices over a DisplayPort (DP)-based link and a processor to generate signals for communication over the DP-based link. The apparatus also includes memory with instructions to cause the processor to initiate a transition to a low power state in devices of the DP-based link by transmitting a sleep pattern signal over the DP-based link, and initiate a transition to an active power state in devices of the DP-based link by transmitting a wake pulse sequence and physical link establishment signal pattern over the DP-based link.

Abstract: A processor module comprises an integrated circuit component attached to a power interposer. One or more voltage regulator modules attach to the power interposer via interconnect sockets and the power interposer routes regulated power signals generated by the voltage regulator modules to the integrated circuit component. Input power signals are provided to the voltage regulator from the system board via straight pins, a cable connector, or another type of connector. The integrated circuit component's I/O signals are routed through the power interposer to a system board via a socket located between the power interposer and the socket. Not having to route regulated power signals from a system board through a socket to an integrated circuit component can result in a system board with fewer layers, which can reduce overall system cost, as well as creating more area available in the remaining layers for I/O signal entry to the socket.

Abstract: Disclosed herein are line patterning techniques for integrated circuit (IC) devices, as well as related devices and assemblies In some embodiments, a patterned line region of an IC device may include: a first conductive line; a second conductive line parallel to the first conductive line; a conductive bridge between the first conductive line and the second conductive line, wherein the conductive bridge is coplanar with the first conductive line and the second conductive line; and pitch-division artifacts.

Abstract: This disclosure describes systems, methods, and devices related to efficient poll response frame in wireless communications. A device may cause to send a multiuser location trigger frame of subtype poll to one or more initiating station devices (ISTAs) in a multi-user trigger-based range measurement during a polling phase. The device may identify a first clear to send (CTS) frame received from a first ISTA of the one or more ISTAs during the polling phase. The device may identify a second CTS frame received from a second ISTA of the one or more ISTAs during the polling phase. The device may determine the identity of a first ISTA based on information comprised in the first CTS frame received from the first ISTA. The device may determine the identity of the second ISTA based on information comprised in the second CTS frame received from the second ISTA.

Abstract: This disclosure describes systems, methods, and devices related to using enhanced acknowledgment and power save. A device may determine a multi-user (MU) multiple-input multiple-output (MIMO) frame associated with a MU-MIMO group. The device may determine a first portion of the MU-MIMO frame associated with the first station device of the MU-MIMO group, wherein the first portion comprises a first indication of a first time offset associated with the first station device. The device may determine a second portion of the MU-MIMO frame associated with the second station device of the MU-MIMO group, wherein the second portion comprises a second indication of a second time offset associated with the second station device. The device may cause to send the MU-MIMO frame to the MU-MIMO group. The device may identify a first acknowledgment from the first station device based on the first time offset.

Abstract: A mechanism is described for facilitating localized load-balancing for processors in computing devices. A method of embodiments, as described herein, includes facilitating hosting, at a processor of a computing device, a local load-balancing mechanism. The method may further include monitoring balancing of loads at the processor and serving as a local scheduler to maintain de-centralized load-balancing at the processor and between the processor and other one or more processors.

Abstract: Described herein are three-dimensional nanoribbon-based logic ICs that include one of more of 1) individual gate control in a vertical stack of nanoribbons, 2) inter-ribbon interconnects in a vertical stack of nanoribbons, and 3) both P- and N-type nanoribbons in a vertical stack of nanoribbons. Using one or more of these features may help realize unique monolithic 3D logic architectures that were not possible with conventional logic circuits and may allow realizing logic devices with favorable metrics in terms of power and performance while preserving the substrate area and cost.

Abstract: An apparatus and method are described, which prior to an event that could result in frequency overshoot, sends a signal to a voltage regulator or generator requesting a temporary supply voltage and/or current boost. This enables a clocking source, such as a phase locked loop (PLL) to lock fast while not needing any long-term voltage guard bands. The apparatus and scheme allows for on-the-fly change in supply voltage and/or clock frequency for a processor with little to no impact on Vmin. During the clock frequency overshoot, the supply voltage is temporarily boosted and then reduced down to the expected voltage level of the power supply. Such boost allows for absorbing the clock frequency overshoot impact. The supply voltage level can be reduced in a step-wise fashion to avoid any potential undershoot in clock frequency.

Abstract: A processing apparatus is provided comprising a multiprocessor having a multithreaded architecture. The multiprocessor can execute at least one single instruction to perform parallel mixed precision matrix operations. In one embodiment the apparatus includes a memory interface and an array of multiprocessors coupled to the memory interface. At least one multiprocessor in the array of multiprocessors is configured to execute a fused multiply-add instruction in parallel across multiple threads.

Abstract: A performance monitor provides cache miss stall and memory bandwidth usage metric samples to a resource exhaustion detector. The detector can detect the presence of last-level cache and memory bandwidth exhaustion conditions based on the metric samples. If cache miss stalls and memory bandwidth usage are both trending up, the detector reports a memory bandwidth exhaustion condition to a resource controller. If cache miss stalls are trending up and memory bandwidth usage is trending down, the detector reports a last-level cache exhaustion condition to the resource controller. The resource controller can allocate additional last-level cache or memory bandwidth to the processor unit to remediate the resource exhaustion condition. If bandwidth-related metric samples indicate that a processor unit may be overloaded due to receiving high bandwidth traffic, the resource controller can take a traffic rebalancing remedial action.

Abstract: This disclosure describes systems, methods, and computer-readable media related to cross indication of queue size in a reverse direction protocol. In some embodiments, a reverse direction (RD) grantor may transmit a frame to an RD responder. The RD responder may identify data to be transmitted to the RD grantor based on the received frame. The RD responder may generate a frame that may comprise a plurality of sub-frames. The RD responder may set a sub-field in each of the sub-frames indicating whether there is data to transmit. The RD responder may also set a second sub-field that may indicate a priority or traffic stream associated with the data to be transmitted. The RD responder may transmit the frame (and associated sub-frames) to the RD grantor.

Abstract: A decoder circuit that supports non-linear precoded signals is disclosed. The decoder circuit comprises a modulo estimation circuit configured to receive a non-linear pre-coded quadrature amplitude modulated (QAM) data symbol and determine a modulo shift estimate associated with the received QAM data symbol, wherein the modulo shift estimate comprises a modulo shift that brings the received QAM symbol within the predetermined QAM constellation. The decoder circuit further comprises a QAM decoder circuit configured to map the received QAM data symbol to a winning constellation point, wherein the winning constellation point comprises a constellation point in an extended QAM constellation associated with the predetermined QAM constellation, and determine a quantized constellation point comprising a constellation point within the predetermined QAM constellation from the winning constellation point, based on applying the modulo shift corresponding to the modulo shift estimate to the winning constellation point.

Abstract: In one embodiment, a processor includes: one or more cores to execute instructions; at least one cache memory; and a coherence circuit coupled to the at least one cache memory. The coherence circuit may have a direct memory access circuit to receive a write request, and based at least in part on an address of the write request, to directly send the write request to a device coupled to the processor via a first bus, to cause the device to store data of the write request to a device-attached memory. Other embodiments are described and claimed.