Abstract: Various systems and methods for providing a wellness mirror are provided herein. A system for providing a wellness mirror includes a display; a modeler to receive depth images from a depth camera that is communicatively coupled to the system, and provide a model of a subject in the depth images; a health profiler to analyze the model and produce a health and wellness analysis; and a user interface to present the health and wellness analysis on the display.

Abstract: Embodiments include apparatuses, methods, and systems for computer assisted or autonomous driving (CA/AD). An apparatus for CA/AD may include a sensor interface, a communication interface, and a driving strategy unit. The sensor interface may receive sensor data indicative of friction between a road surface of a current location of a CA/AD vehicle and one or more surfaces of one or more tires of the CA/AD vehicle. The communication interface may receive, from an external road surface condition data source, data indicative of friction for a surface of a road section ahead of the current location of the CA/AD vehicle. The driving strategy unit may determine, based at least in part on the sensor data and the data received from the external road surface condition data source, a driving strategy for the CA/AD vehicle beyond the current location of the CA/AD vehicle. Other embodiments may also be described and claimed.

Abstract: An embodiment of a semiconductor package apparatus may include technology to associate an asset to a fixture with a device positioned proximate to the fixture, and determine a location of the fixture based on a location of the device. Other embodiments are disclosed and claimed. Non-limiting example applications may include shipping, logistics, warehouse asset tracking, retail, etc.

Abstract: An integrated circuit of an aspect includes a power control unit having an interface to receive an indication that one or more instructions of a first type are to be performed by a core. The power control unit also has logic to control a maximum clock frequency for the core based on the indication that the instructions of the first type are to be performed by the core.

Abstract: Systems and methods of determining a device position are described. GPS and cellular signals, in addition to VIO displacement are used to determine the device position via a loose or tight coupling algorithm. Both algorithms iteratively linearize base station position equations around an intermediate position that changes each iteration based on VIO displacement and solves the linearized solutions until convergence. The loose coupling algorithm uses the GPS fix as an initiation position, linearizing and solving using the base station equations only. The tight coupling algorithm linearizes both the base station and GPS position equations, using an arbitrary initial position. To account for multipath effects, the linearization and solution are performed for multiple random sets of measurements and the position with the smallest error metric is selected.

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.

Abstract: Methods and apparatuses for safety enhanced computer-assisted driving. In embodiments, an apparatus for computer-assisted driving may include a neural network to determine a classification for behavior of a driver of a vehicle having the apparatus, based at least in part on data about the vehicle collected in real time, and a current level of stress or drowsiness of the driver determined in real time; and a safety action engine coupled to the neural network to determine a safety related action, based at least in part on the determined driver behavior classification and data related to current traffic or road condition of a route the vehicles is currently traveling on. The safety related action may be performed by an infotainment system or a navigation system of the vehicle to assist the driver in driving the vehicle in a safer manner.

Abstract: One embodiment provides for a processor comprising a three-dimensional (3D) integrated circuit stack including multiple graphics processor cores and interconnect logic to interconnect the graphics processor cores of the 3D integrated circuit stack to enable data distribution between the graphics processor cores over a virtual channel including multiple programmatically pre-assigned traffic classifications.

Abstract: Components, devices, systems, and methods for providing a movable haptic actuator for a user interacting with a simulated environment. The simulated environment may be virtual reality, augmented reality, or mixed reality. A fastener may be used to couple the haptic actuator to a wearable article worn by the user. The haptic actuator communicates with a controller to receive information to provide feedback to the user during operations of the simulated environment. The haptic actuator may be movable from a first position on the wearable article to a second position.

Abstract: Embodiments of the present disclosure describe a semiconductor multi-gate transistor having a semi-conductor fin extending from a substrate and including a sub-fin region and an active region. The sub-fin region may include a dielectric material region under the gate to provide improved isolation. The dielectric material region may be formed during a replacement gate process by replacing a portion of a sub-fin region under the gate with the dielectric material region, followed by fabrication of a replacement gate structure. The sub-fin region may be comprised of group III-V semiconductor materials in various combinations and concentrations. The active region may be comprised of a different group III-V semiconductor material. The dielectric material region may be comprised of amorphous silicon. Other embodiments may be described and/or claimed.

Abstract: A system-in-package includes a package substrate that at least partially surrounds an embedded radio-frequency integrated circuit chip and a processor chip mated to a redistribution layer. A wide-band phased-array antenna module is mated to the package substrate with direct interconnects from the radio-frequency integrated circuit chip to antenna patches within the antenna module. Additionally, fan-out antenna pads are also coupled to the radio-frequency integrated circuit chip.

Abstract: Nanowire structures having non-discrete source and drain regions are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate. Each of the nanowires includes a discrete channel region disposed in the nanowire. A gate electrode stack surrounds the plurality of vertically stacked nanowires. A pair of non-discrete source and drain regions is disposed on either side of, and adjoining, the discrete channel regions of the plurality of vertically stacked nanowires.

Abstract: An apparatus and method for sampling pattern generation in a ray tracing architecture. For example, one embodiment of a graphics processing apparatus comprises: a ray generation circuit to generate a ray stream from one or more image tiles; and a sample pattern generation circuit to generate samples for rays in the ray stream, the samples generated to exhibit at least some randomness across pixels of a given frame but be repeatable across multiple frames.

Abstract: Techniques and mechanisms for determining a latency event to be represented in performance monitoring information. In an embodiment, circuit blocks of a pipeline experience respective latency events at variously times during tasks by the pipeline which service a workload. The circuit blocks send to an evaluation circuit of the pipeline respective event signals which each indicate whether a respective latency event has been detected. The event signals are communicated in parallel with at least a portion of the pipeline. In response to a trigger event in the pipeline, the evaluation circuit selects an event signal, based on relative priorities of the event signals, which provides a sample indicating a detected latency event. Based on the selected event signal, a representation of the indicated latency event in provided to latency event count or other value performance monitoring information. In another embodiment, different time delays are applied to various event signals.

Abstract: Techniques for high-fidelity three-dimensional (3D) reconstruction of a dynamic scene as a set of voxels are provided. One technique includes: receiving, by a processor, image data from each of two or more spatially-separated sensors observing the scene from a corresponding two or more vantage points; generating, by the processor, the set of voxels from the image data on a frame-by-frame basis; reconstructing, by the processor, surfaces from the set of voxels to generate low-fidelity mesh data; identifying, by the processor, performers in the scene from the image data; obtaining, by the processor, high-fidelity mesh data corresponding to the identified performers; and merging, by the processor, the low-fidelity mesh data with the high-fidelity mesh data to generate high-fidelity 3D output. The identifying of the performers includes: segmenting, by the processor, the image data into objects; and classifying, by the processor, those of the objects representing the performers.

Abstract: An apparatus and method for scalable interrupt reporting.

Abstract: An apparatus and method are described for performing an early depth test on graphics data. For example, one embodiment of a graphics processing apparatus comprises: early depth test circuitry to perform an early depth test on blocks of pixels to determine whether all pixels in the block of pixels can be resolved by the early depth test; a plurality of execution circuits to execute pixel shading operations on the blocks of pixels; and a scheduler circuit to schedule the blocks of pixels for the pixel shading operations, the scheduler circuit to prioritize the blocks of pixels in accordance with the determination as to whether all pixels in the block of pixels can be resolved by the early depth test.

Abstract: Described is an apparatus which comprises: a time-to-digital converter (TDC) to receive a reference clock and a feedback clock, wherein the TDC is to generate a digital output code representing a time difference between the reference clock and the feedback clock; a circuitry to apply a digital code to an output of the TDC; and a node to receive the digital output code from the TDC and the digital code from the circuitry, wherein the circuitry is to monitor the digital output code and to control the TDC according to at least the monitored digital output code.

Abstract: Systems and methods for container access to graphics processing unit (GPU) resources are disclosed herein. In some embodiments, a computing system may include a physical GPU and kernel-mode driver circuitry, to communicatively couple with the physical GPU to create a plurality of emulated GPUs and a corresponding plurality of device nodes. Each device node may be associated with a single corresponding user-side container to enable communication between the user-side container and the corresponding emulated GPU. Other embodiments may be disclosed and/or claimed.

Abstract: Techniques are disclosed for forming integrated circuit structures including a magnetic tunnel junction (MTJ), such as spin-transfer torque memory (STTM) devices, having magnetic contacts. The techniques include incorporating an additional magnetic layer (e.g., a layer that is similar or identical to that of the magnetic contact layer) such that the additional magnetic layer is coupled antiferromagnetically (or in a substantially antiparallel manner). The additional magnetic layer can help balance the magnetic field of the magnetic contact layer to limit parasitic fringing fields that would otherwise be caused by the magnetic contact layer. The additional magnetic layer may be antiferromagnetically coupled to the magnetic contact layer by, for example, including a nonmagnetic spacer layer between the two magnetic layers, thereby creating a synthetic antiferromagnet (SAF).