Abstract: First and second circuits in an integrated circuit that generate local hot spots are activated at different times in order to reduce heat generation within each of the first and second circuits. The first and second circuits in the integrated circuit have the same circuit architecture. The first circuit processes data during a first time period, and heat generation is reduced in the second circuit during the first time period. A data path of the data is then switched from the first circuit to the second circuit. The second circuit then processes the data during a second time period after the first time period, and heat generation is reduced in the first circuit during the second time period. The data path of the data is then switched from the second circuit back to the first circuit. The first circuit then processes the data again.

Abstract: An integrated circuit configured to execute multiple operations in parallel is provided. The integrated circuit may be organized into multiple logic sectors. Two or more groups of logic sectors may be executed in an interleaved fashion, where successive groups of logic sectors are activated after a predetermined amount of delay. The integrated circuit may include an array of memory cells. Rows of the memory cells may be accessed in an interleaving manner, where successive rows of memory cells are selected after a predetermined amount of delay. Operating groups of circuit components using an interleaving scheme can help improve operational efficiency while reducing power supply noise without having to increase die area for on-die decoupling capacitance.

Abstract: Particular embodiments described herein provide a keycap that includes a plurality of front plane elements, where each front plane element includes a top electrode, a conductive region under each of the plurality of front plane elements, where each conductive region includes a bottom electrode and a top electrode coupling area, where each top electrode coupling area is electrically coupled to a common top electrode node, an electrical path between each top electrode and each corresponding top electrode coupling area such that each top electrode is connected to the common top electrode node, and a dielectric between each top electrode and each bottom electrode.

Abstract: Electronic devices and methods including a printed circuit board configured to accept CPUs and memory modules are described. One apparatus includes a printed circuit board that includes a first row of elements including a first CPU positioned between first and second groups of dual in-line memory modules (DIMMs). The printed circuit board also includes a second row of elements including a second CPU positioned between third and fourth groups of DIMMs. The apparatus also includes a third row of elements including a fifth group of DIMMs, wherein the second row of elements is positioned between the first row of elements and the third row of elements. Other embodiments are described and claimed.

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive, in a read/modify/write (RMW) pipeline, a cache access request from a requestor, wherein the cache request comprises a cache set identifier associated with requested data in the cache set, determine whether the cache set associated with the cache set identifier is in an inaccessible invalid state, and in response to a determination that the cache set is in an inaccessible state or an invalid state, to terminate the cache access request. Other embodiments are also disclosed and claimed.

Abstract: In one embodiment a graphics processing system comprises a graphics processor having execution logic and shared memory and a shader compiler unit to compile a shader program for execution by the execution logic of the graphic processor, wherein the shader is to optimize the shader program during the compile, wherein to optimize the shader program includes to convert a divergent block of parallel instructions into a divergent block and a non-divergent block of instructions.

Abstract: A processing system includes a processor and a VM-to-VM communication accelerator circuit comprising a first interface device to support direct memory access (DMA) data transfers by the first VM, a register to store a reference to a primary physical function (PF) associated with the first interface device, wherein the first primary PF is associated with an access control table (ACT) specifying an access permission for the first VM with respect to a second VM, and a direct memory access (DMA) descriptor processing circuit to process, using a working queue associated with the first primary PF, a DMA descriptor referencing a request for a DMA data transfer between the first VM and the second VM, and execute, using the first interface device, the DMA data transfer based on the access permission.

Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.

Abstract: Generally discussed herein are systems, devices, and methods for data management in a reverse content data network (rCDN). A component of the rCDN may include a memory to hold content received from a first sensor device of a plurality of sensor devices of the rCDN and first attributes that describe properties of the content. The component may include processing circuitry to receive second content from a second sensor device of the plurality of sensor devices, the second content including a plurality of second attributes that describe properties of the second content, and forward, in response to a determination, based on the first and second attributes, that there is insufficient space to store the second content on the memory, the second content to a node of the rCDN that is fewer hops away from a backend cloud than the component.

Abstract: In some examples, a power delivery system includes a primary power path to provide power to a computing system. The power delivery system also includes a bypass power path. A port manager is to disable the primary power path and to enable the bypass power path in response to a dead battery condition.

Abstract: A touch panel for a display may include a touch sensor with a plurality of electrode traces. A first portion of the plurality of electrode traces may form sensing lines configured to receive touch input. The touch sensor includes an edge dummy area between an edge of the touch sensor and an electrode trace of a remaining portion of the plurality of electrode traces. The edge dummy area may be located outside of the sensing lines. The touch panel may further include an antenna with a radiation structure and a ground structure. The radiation structure may be located within a routing traces area outside of the touch sensor. The ground structure may be located within the edge dummy area. The ground structure may include an electrode trace of the plurality of electrode traces located within the edge dummy area of the touch sensor.

Abstract: In some examples, a system can include a microcontroller to initialize a counter to a predetermined value for each image component of an image data slice. The microcontroller can also store a number of received bits for each image component in a data structure and generate a pre-allocation signal indicating that additional bits of data for one of the image components are to be requested and stored in the data structure, wherein the pre-allocation signal is to be generated in response to determining that the counter is below the predetermined value. The microcontroller can also increase the counter by the predetermined value and transmit an address from the data structure to a display device in response to detecting a valid signal.

Abstract: Methods and systems to display, in real time, detailed attribute information regarding a calling party. This information may be presented to a user in conjunction with an incoming voice-call or message on the user's smartphone/mobile internet device (MID) or other mobile device. Such information can help him/her in real-time to decide whether to respond to the communication. Attribute information is collected at a caller attributes processing server and communicated to a receiver device of the called party.

Abstract: In one embodiment, a processor comprises a first prefetcher to generate prefetch requests to prefetch data into a mid-level cache; a second prefetcher to generate prefetch requests to prefetch data into the mid-level cache; and a prefetcher selector to select a prefetcher configuration for the first prefetcher and the second prefetcher based on at least one memory access metric, wherein the prefetcher configuration is to specify whether the first prefetcher is to be enabled to issue, to the mid-level cache, prefetch requests for data of a particular page and whether the second prefetcher is to be enabled to issue, to the mid-level cache, prefetch requests for data of the particular page.

Abstract: An first apparatus is provided which comprises: a first port coupled to a second port of a second apparatus; first one or more circuitries to monitor current of a power bus that is to supply power from the first port to the second port; and second one or more circuitries to: while the first port is to operate in a high-current mode of operation, determine that the current of the power bus is less than a threshold current; and cause the first port to enter a suspend mode of operation from the high-current mode of operation, in response to the current of the power bus being less than the threshold current.

Abstract: A system, article, and method of 3D reconstruction with volume-based filtering for image processing.

Abstract: Embodiments may relate to a dielectric waveguide that includes a substrate and a waveguide material disposed within the substrate. The dielectric waveguide may further include a waveguide launcher electromagnetically and physically coupled with the waveguide material, wherein the waveguide launcher is exposed at a side of the dielectric substrate. Other embodiments may be described or claimed.

Abstract: An apparatus to facilitate pixel compression is disclosed. The apparatus includes a rasterizer module to convert an image to a plurality of pixels, an interface coupled to the rasterizer module, a depth check module coupled to the interface and compression logic to perform a compression encoding on the plurality of pixels, including dividing the plurality of pixels into a mega pixel block having a plurality of pixel blocks, determining coverage information for pixels in each of the plurality of pixel blocks, encoding each of the plurality of pixel blocks based on the coverage information to generate a mega encoded block.

Abstract: A mechanism to provide visual feedback regarding computing system command gestures. An embodiment of an apparatus includes a sensing element to sense a presence or movement of a user of the apparatus, a processor, wherein operation of the processor includes interpretation of command gestures of a user to provide input to the apparatus; and a display screen, the apparatus to display one or more icons on the display screen, the one or more icons being related to the operation of the apparatus. The apparatus is to display visual feedback for a user of the apparatus, visual feedback including a representation of one or both hands of the user while the one or both hands are within a sensing area for the sensing element.

Abstract: Techniques are disclosed for transistor gate trench engineering to decrease capacitance and resistance. Sidewall spacers, sometimes referred to as gate spacers, or more generally, spacers, may be formed on either side of a transistor gate to help lower the gate-source/drain capacitance. Such spacers can define a gate trench after dummy gate materials are removed from between the spacers to form the gate trench region during a replacement gate process, for example. In some cases, to reduce resistance inside the gate trench region, techniques can be performed to form a multilayer gate or gate electrode, where the multilayer gate includes a first metal and a second metal above the first metal, where the second metal includes lower electrical resistivity properties than the first metal. In some cases, to reduce capacitance inside a transistor gate trench, techniques can be performed to form low-k dielectric material on the gate trench sidewalls.