Abstract: An example system for generating stereoscopic light field panoramas includes a receiver to receive a plurality of synchronized images. The system also includes a calibrator and projector to calibrate the synchronized images, undistort the synchronized images, and project the undistorted images to a sphere to generate undistorted rectilinear images. The system further includes a disparity estimator to estimate a disparity between neighboring views of the undistorted rectilinear images to determine an optical flow between the undistorted rectilinear images. The system includes a view interpolator to perform in-between view interpolation on the undistorted rectilinear images based on the optical flow. The system also further includes a light field panorama generator to generate a stereoscopic light field panorama for a plurality of perspectives using concentric viewing circles.
Abstract: Embodiments may relate to a transceiver chip. The transceiver chip may include a substrate that has a first transceiver component and a second transceiver component positioned therein. The transceiver chip may further include a well material that is positioned between the first transceiver component and the second transceiver component. The well material may mitigate cross-talk between the first transceiver component and the second transceiver component. Other embodiments may be described or claimed.
Abstract: Techniques related to implementing an always on face detection architecture at ultra low power are discussed. Such techniques include updating a face detection model at a host processor using positive and/or negative validation of face detection results from an always on microcontroller operating at ultra low power.
Abstract: There is disclosed in an example, a gallium nitride (GaN) field effect transistor (FET) having a gate, a drain, and a source, having: a doped GaN buffer layer; a first epitaxy layer above the buffer layer, the first epitaxy layer having a first doping profile (for example, doped, or p-type doping); and a second epitaxy layer above the first epitaxy layer, the second epitaxy layer having a second doping profile (for example, undoped, or n-type doping).
Abstract: Described are mechanisms for depth sensor optimization based on detected distances. The mechanisms may comprise a distance measurement module, which may be operable to measure a physical distance between a 3D camera sensor and a person or object in view of the 3D camera. The mechanisms may also comprise a sensor mode selector module, which may be operable to select a best camera sensor configuration based on a measured distance from a distance-measurement module.
Abstract: An example apparatus for displaying stereo elemental images includes two coupled eyepieces. Each of the two eyepieces also includes a curved screen to display a number of elemental images. Each of the two eyepieces also includes a curved lens array concentrically displaced in front of the curved screen to magnify the elemental images. Each of the number of elemental images is magnified by a different lens in the curved lens array.
Type:
Application
Filed:
September 19, 2017
Publication date:
March 21, 2019
Applicant:
INTEL CORPORATION
Inventors:
Joshua J. Ratcliff, Alexey M. Supikov, Santiago E. Alfaro, Basel Salahieh
Abstract: In an example, there is disclosed a chemical compound, including a transition metal, a post-transition metal, a metalloid, and a nonmetal. By way of non-limiting example, the post-transition metal may be aluminum. The transition metal is selected from the group consisting of tungsten, tantalum, hafnium, molybdenum, niobium, zirconium, vanadium, and titanium. The metalloid may be boron or silicon. The nonmetal may be carbon or nitrogen. The compound may be used, for example, as a barrier material in an integrated circuit.
Type:
Application
Filed:
March 31, 2016
Publication date:
March 21, 2019
Applicant:
Intel Corporation
Inventors:
Daniel J. Zierath, Jason A. Farmer, Daniel B. Bergstrom
Abstract: Systems, apparatuses and methods of monitoring the utilization of protective equipment by individuals requesting access to a restricted area that requires the use of specific protective equipment, are provided. A protective equipment checker, which includes a proximity sensor, a three-dimensional (3D) camera, and a radio-frequency identification (RFID) reader, performs a full body scan on the individual to determine if the location-specific protective equipment is being worn, or is in the possession of the individual. If a determination is made that the proper protective equipment is being worn, the individual is granted access to the location. If, one the other hand, the required protective equipment is not being worn, entry to the location is denied.
Type:
Application
Filed:
March 25, 2016
Publication date:
March 21, 2019
Applicant:
Intel Corporation
Inventors:
Elizabeth Stortstrom, Andrew Larson, Mark E. Sprenger, Ralph V. Miele
Abstract: Systems and methods are provided that tune a convolutional neural network (CNN) to increase both its accuracy and computational efficiency. In some examples, a computing device storing the CNN includes a CNN tuner that is a hardware and/or software component that is configured to execute a tuning process on the CNN. When executing according to this configuration, the CNN tuner iteratively processes the CNN layer by layer to compress and prune selected layers. In so doing, the CNN tuner identifies and removes links and neurons that are superfluous or detrimental to the accuracy of the CNN.
Type:
Application
Filed:
September 18, 2017
Publication date:
March 21, 2019
Applicant:
Intel Corporation
Inventors:
Seok-Yong Byun, Byungseok Roh, Minje Park, Byoungwon Choe
Abstract: An embodiment of an extensible memory hub may include one or more upstream interface ports to couple the extensible memory hub to the controller, one or more downstream interface ports to couple the extensible memory hub to one or more of the nonvolatile memory and another extensible memory hub, and a clock circuit to provide a first clock signal at a first frequency to the one or more upstream interface ports and a second clock signal at a second frequency to the one or more downstream interface ports, where the first frequency may be different from the second frequency. Other embodiments are disclosed and claimed.
Abstract: One embodiment provides a four stable state neuron. The four stable state neuron includes a plurality of input elements and a plurality of coupling channels. Each input element is coupled to a respective coupling channel and each input element is to scale a respective two-dimensional input signal by a weight. The four stable state neuron further includes a first output element coupled to the plurality of coupling channels. The first output element is to receive the plurality of weighted two-dimensional input signals and to generate a two-dimensional output signal based, at least in part, on a threshold value.
Type:
Application
Filed:
April 1, 2016
Publication date:
March 21, 2019
Applicant:
Intel Corporation
Inventors:
Sasikanth Manipatruni, Ian A. Young, Dmitri E. Nikonov
Abstract: In some examples, display backlight strings are grouped into at least two groups based on characteristics of the display backlight strings. A first of the at least two groups of display backlight strings is operated at a first operating voltage. A second of the at least two groups of display backlight strings is operated at a second operating voltage.
Type:
Application
Filed:
September 21, 2017
Publication date:
March 21, 2019
Applicant:
INTEL CORPORATION
Inventors:
Vijayakumar A. Dibbad, Mallari C. Hanchate
Abstract: A method for efficient frame loss recovery and reconstruction (EFLRR) in a dyadic hierarchy is described herein. The method includes obtaining a current frame of a group of pictures. The method also includes calculating a Dyadic Hierarchy Picture Index difference based on a layer information in response to a prior frame missing in the group of pictures. Finally, the method includes decoding the current frame in response to a determined frame continuity based on the Dyadic Hierarchy Picture Index difference.
Type:
Application
Filed:
September 21, 2017
Publication date:
March 21, 2019
Applicant:
INTEL CORPORATION
Inventors:
Prasanna Kumar Mandapadi Ramasubramanian, Rajesh Poornachandran, Sri Ranjan Srikantam
Abstract: Techniques related to coding video using adaptive quantization rounding offsets for use in transform coefficient quantization are discussed. Such techniques may include determining the value of a quantization rounding offset for a picture of a video sequence based on evaluating a maximum coding bit limit of the picture, a quantization parameter of the picture, and parameters corresponding to the video.
Type:
Application
Filed:
November 19, 2018
Publication date:
March 21, 2019
Applicant:
Intel Corporation
Inventors:
Ximin Zhang, Sang-hee Lee, Keith W. Rowe
Abstract: An example system for lightweight view dependent rendering is described herein. The system includes a processor configured to determine a moving region of each camera view, wherein the moving region is defined by a bounding box and track each moving region to obtain a plurality of cropped videos for each camera view. The system may also be configured to generate a billboard for each camera view and render each billboard.
Abstract: An apparatus is provided which comprises: a plurality of data routers to route data packets, wherein the plurality of data routers comprises: a first data router comprising a trace port, and a second data router coupled to a component; and one or more trace routers to route trace information of the apparatus, wherein a first trace router of the one or more trace routers is coupled to the trace port, and wherein the first trace router is to route configuration information from the component to the trace port, the configuration information to configure the trace port.
Type:
Application
Filed:
September 19, 2017
Publication date:
March 21, 2019
Applicant:
Intel Corporation
Inventors:
Simona Bernardi, Helmut Reinig, Todor M. Mladenov
Abstract: This disclosure describes systems, devices, methods and computer readable media for enhanced network communication for use in higher performance applications including storage, high performance computing (HPC) and Ethernet-based fabric interconnects. In some embodiments, a network controller may include a transmitter circuit configured to transmit packets on a plurality of virtual lanes (VLs), the VLs associated with a defined VL priority and an allocated share of network bandwidth. The network controller may also include a bandwidth monitor module configured to measure bandwidth consumed by the packets and an arbiter module configured to adjust the VL priority based on a comparison of the measured bandwidth to the allocated share of network bandwidth. The transmitter circuit may be further configured to transmit the packets based on the adjusted VL priority.
Type:
Grant
Filed:
February 18, 2015
Date of Patent:
March 19, 2019
Assignee:
Intel Corporation
Inventors:
Albert S. Cheng, Thomas D. Lovett, Michael A. Parker
Abstract: Fermi filter field effect transistors having a Fermi filter between a source and a source contact, systems incorporating such transistors, and methods for forming them are discussed. Such transistors may include a channel between a source and a drain both having a first polarity and a Fermi filter between the source and a source contact such that the Fermi filter has a second polarity complementary to the first polarity.
Abstract: The present disclosure provides a programmable integrated circuit die for optical testing. The integrated circuit die includes both photonic and electronic elements. In particular, the integrated circuit die may include a memory block, a programmable logic block (for example, a field programmable gate array), an electrical transceiver block, an optical transceiver block, and an optical test interface unit. The programmable logic block may be programmed to have logic functionalities of an embedded microcontroller and of various encoders/decoders. The logic functions may be soft, hard, or mixed. The memory may be used to store test patterns, look-up tables, measured waveforms, error time profiles and statistics. The electrical and optical transceivers may implement PAMn, NRZ, or QAMn modulations and may have programmable parameters, including: voltage levels; optical power; slew rate; magnitude/phase; clock generation and recovery; equalizations; sampling levels; and sampling times.
Abstract: Technologies for quality of service based throttling in a fabric architecture include a network node of a plurality of network nodes interconnected across the fabric architecture via an interconnect fabric. The network node includes a host fabric interface (HFI) configured to facilitate the transmission of data to/from the network node, monitor quality of service levels of resources of the network node used to process and transmit the data, and detect a throttling condition based on a result of the monitored quality of service levels. The HFI is further configured to generate and transmit a throttling message to one or more of the interconnected network nodes in response to having detected a throttling condition. The HFI is additionally configured to receive a throttling message from another of the network nodes and perform a throttling action on one or more of the resources based on the received throttling message. Other embodiments are described herein.
Type:
Grant
Filed:
April 1, 2016
Date of Patent:
March 19, 2019
Assignee:
Intel Corporation
Inventors:
Francesc Guim Bernat, Karthik Kumar, Thomas Willhalm, Raj K. Ramanujan, Brian J. Slechta