Patents Assigned to Intel Corporations
  • GATE WALLS FOR QUANTUM DOT DEVICES
    Publication number: 20190043955
    Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a first gate and an adjacent second gate above the quantum well stack; and a gate wall between the first gate and the second gate, wherein the gate wall includes a spacer and a capping material, the spacer has a top and a bottom, the bottom of the spacer is between the top of the spacer and the quantum well stack, and the capping material is proximate to the top of the spacer.
    Type: Application
    Filed: September 28, 2018
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventors: Hubert C. George, Ravi Pillarisetty, Lester Lampert, James S. Clarke, Nicole K. Thomas, Roman Caudillo, David J. Michalak, Jeanette M. Roberts
  • TECHNOLOGY TO AUGMENT THREAD SCHEDULING WITH TEMPORAL CHARACTERISTICS
    Publication number: 20190042307
    Abstract: Systems, apparatuses and methods may provide for technology that identifies a thread and selects a core from a plurality of processor cores in response to the selected core being available while satisfying a least used condition with respect to the plurality of processor cores. The technology may also schedule the thread to be executed on the selected core.
    Type: Application
    Filed: August 30, 2018
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventors: Ramakrishnan Sivakumar, Vijay Dhanraj, Russell Fenger, Guy Therien
  • DYNAMIC SLEEP FOR A DISPLAY PANEL
    Publication number: 20190043415
    Abstract: Technology for a display controller is described. The display controller can detect a frame update when the display controller is in a dynamic sleep state. The display controller can wake up from the dynamic sleep state and enter a selective update state at a programmed vertical blanking interrupt (VBI) that precedes an actual VBI. The display controller can perform a scan-out with a display panel during the selective update state. The display controller can return to the dynamic sleep state in a same time frame after the scan-out is completed. The display controller can exclude timing logic to send a VBI at every time frame to the display panel to maintain time synchronization between the display controller and the display panel.
    Type: Application
    Filed: June 29, 2018
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventors: Vishal Sinha, Paul Diefenbaugh, Todd Witter, Jason Tanner, Arthur Runyan, Nausheen Ansari, Kathy Bui, Yifan Li
  • SECURE REPORTING OF PLATFORM STATE INFORMATION TO A REMOTE SERVER
    Publication number: 20190045016
    Abstract: Technologies disclosed herein provide a method for receiving at a device from a remote server, a request for state information from a first processor of the device, obtaining the state information from one or more registers of the first processor based on a request structure indicated by a first instruction of a software program executing on the device, and generating a response structure based, at least in part, on the obtained state information. The method further includes using a cryptographic algorithm and a shared key established between the device and the remote server to generate a signature based, at least in part, on the response structure, and communicating the response structure and the signature to the remote server. In more specific embodiments, both the response structure and the request structure each include a same nonce value.
    Type: Application
    Filed: June 29, 2018
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventors: Prashant Dewan, Siddhartha Chhabra, Uttam K. Sengupta, Howard C. Herbert
  • ASYMMETRICAL EMBEDDED UNIVERSAL SERIAL BUS (EUSB) LINK
    Publication number: 20190042521
    Abstract: A Universal Serial Bus (USB) circuitry of an apparatus is disclosed. In an example, the USB circuitry includes a High Speed (HS) transmitter to transmit data at a first data rate from the apparatus to a component; and a pair of Low Speed/Full speed (LS/FS) receivers to receive data at one or both of a second data rate or a third data rate from the component. In an example, the USB circuitry is to refrain from receiving data from the component at the first data rate.
    Type: Application
    Filed: February 26, 2018
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventors: Huimin Chen, Karthi Vadivelu, Abdul Ismail, Antonio Cheng, Nobuyuki Suzuki
  • Secure Type-Enforced Actions
    Publication number: 20190044939
    Abstract: In some examples, a robot middleware system including a first robot middleware node, a second robot middleware node, and one or more secure encrypted type-enforced context message between the first robot middleware node and the second robot middleware node.
    Type: Application
    Filed: March 30, 2018
    Publication date: February 7, 2019
    Applicant: INTEL CORPORATION
    Inventors: Ned M. Smith, Gregory Burns
  • MOVABLE HAPTIC ACTUATOR
    Publication number: 20190043321
    Abstract: Components, devices, systems, and methods for providing a movable haptic actuator for a user interacting with a simulated environment. The simulated environment may be virtual reality, augmented reality, or mixed reality. A fastener may be used to couple the haptic actuator to a wearable article worn by the user. The haptic actuator communicates with a controller to receive information to provide feedback to the user during operations of the simulated environment. The haptic actuator may be movable from a first position on the wearable article to a second position.
    Type: Application
    Filed: June 29, 2018
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventors: Sanjay Aghara, Samarth Alva, Arvind S, Sean J. Lawrence, Raghavendra Angadimani, Satyajit Siddharay Kamat
  • QUANTUM DOT DEVICES WITH PASSIVE BARRIER ELEMENTS IN A QUANTUM WELL STACK BETWEEN METAL GATES
    Publication number: 20190043950
    Abstract: A quantum dot device is disclosed that includes a quantum well stack, a first and a second plunger gates above the quantum well stack, and a passive barrier element provided in a portion of the quantum well stack between the first and the second plunger gates. The passive barrier element may serve as means for localizing charge in the quantum dot device and may be used to replace charge localization control by means of a barrier gate. In general, a quantum dot device with a plurality of plunger gates provided over a given quantum well stack may include a respective passive barrier element between any, or all, of adjacent plunger gates in the manner as described for the first and second plunger gates.
    Type: Application
    Filed: September 27, 2018
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventors: Hubert C. George, Ravi Pillarisetty, Lester Lampert, James S. Clarke, Nicole K. Thomas, Roman Caudillo, David J. Michalak, Jeanette M. Roberts
  • VIEW INTERPOLATION OF MULTI-CAMERA ARRAY IMAGES WITH FLOW ESTIMATION AND IMAGE SUPER RESOLUTION USING DEEP LEARNING
    Publication number: 20190045168
    Abstract: Techniques related to interpolating an intermediate view image from multi-view images are discussed. Such techniques include downsampling first and second images that represent a view of a scene, generating a disparity map based on applying a first CNN to the downscaled first and second images, translating the downscaled first and second images using the disparity map, applying a second CNN to the translated downscaled first and second images and the disparity map to generate a downscaled intermediate image, and upscaling the downscaled intermediate image to an intermediate image at the resolution of the first and second images using an image super-resolution convolutional neural network.
    Type: Application
    Filed: September 25, 2018
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventors: Bindita Chaudhuri, Fan Zhang, Oscar Nestares
  • METHODS AND ARRANGEMENTS TO MANAGE MEMORY IN CASCADED NEURAL NETWORKS
    Publication number: 20190042925
    Abstract: Logic may reduce the size of runtime memory for deep neural network inference computations. Logic may determine, for two or more stages of a neural network, a count of shared block allocations, or shared memory block allocations, that concurrently exist during execution of the two or more stages. Logic may compare counts of the shared block allocations to determine a maximum count of the counts. Logic may reduce inference computation time for deep neural network inference computations. Logic may determine a size for each of the shared block allocations of the count of shared memory block allocations, to accommodate data to store in a shared memory during execution of the two or more stages of the cascaded neural network. Logic may determine a batch size per stage of the two or more stages of a cascaded neural network based on a lack interdependencies between input data.
    Type: Application
    Filed: April 17, 2018
    Publication date: February 7, 2019
    Applicant: INTEL CORPORATION
    Inventors: Byoungwon Choe, Kwangwoong Park, Seokyong Byun
  • DETECTION AND REDUCTION OF WIND NOISE IN COMPUTING ENVIRONMENTS
    Publication number: 20190043520
    Abstract: A mechanism is described for facilitating wind detection and wind noise reduction in computing environments according to one embodiment. An apparatus of embodiments, as described herein, includes wind detection logic to detect wind associated with the apparatus including a wearable computing device, wherein the wind is detected based on samples from multiple microphones and extraction and use of multiple features including spectral sub-band centroid (SSC) features and coherence features; and decision and execution logic to reduce wind noise associated with the detected wind.
    Type: Application
    Filed: March 30, 2018
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventors: Swarnendu Kar, Anthony Rhodes
  • Apparatus to Synchronize Clocks of Configurable Integrated Circuit Dies Through an Interconnect Bridge
    Publication number: 20190044520
    Abstract: An IC, operable at a first clock phase, includes first and second IOs and a PLL. The PLL includes a control circuit, an input to receive a first clock signal, an output to output a second clock signal, and a first detector to generate a first phase difference signal from the first and second clock signals. The IC includes a second phase detector that is coupled to the PLL's output to receive the second clock signal and is coupled to the first IO to receive a third clock single from a second IC, which is operable at a second clock phase. The second detector generates a second phase difference signal from the second and third clock signals. If the PLL uses the second phase difference signal to generate the second clock signal, then the second clock signal is synchronized with the third clock signal for synchronous data transfer.
    Type: Application
    Filed: June 29, 2018
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventors: Lai Guan Tang, Ankireddy Nalamalpu, Dheeraj Subbareddy
  • NANOWIRE TRANSISTOR FABRICATION WITH HARDMASK LAYERS
    Publication number: 20190043948
    Abstract: A nanowire device of the present description may be produced with the incorporation of at least one hardmask during the fabrication of at least one nanowire transistor in order to assist in protecting an uppermost channel nanowire from damage that may result from fabrication processes, such as those used in a replacement metal gate process and/or the nanowire release process. The use of at least one hardmask may result in a substantially damage free uppermost channel nanowire in a multi-stacked nanowire transistor, which may improve the uniformity of the channel nanowires and the reliability of the overall multi-stacked nanowire transistor.
    Type: Application
    Filed: October 1, 2018
    Publication date: February 7, 2019
    Applicant: INTEL CORPORATION
    Inventors: Seung Hoon Sung, Seiyon Kim, Kelin J. Kuhn, Willy Rachmady, Jack T. Kavalieros
  • NON-VOLATILE MEMORY STRUCTURES AND DEVICES
    Publication number: 20190044063
    Abstract: A memory cell can include a chalcogenide material having a narrowed end. A conductive material can be positioned at the narrowed end of the chalcogenide material. A dielectric barrier layer can be disposed between the conductive material and the narrowed end of the chalcogenide material. A dielectric spacer material can be positioned along a narrowed segment of the chalcogenide material.
    Type: Application
    Filed: March 30, 2018
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventors: Lorenzo Fratin, Russell L. Meyer, Fabio Pellizzer
  • METHOD AND SYSTEM OF LIGHT SOURCE ESTIMATION FOR IMAGE PROCESSING
    Publication number: 20190045162
    Abstract: A system, article, and method to perform light source estimation for image processing includes measuring a compactness of the distribution of the image data to select a light source.
    Type: Application
    Filed: April 10, 2018
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventors: Evgeny KRESTYANNIKOV, Dmytro PALIY
  • COMPILER TRANSFORMATION WITH LOOP AND DATA PARTITIONING
    Publication number: 20190042221
    Abstract: Logic may transform a target code to partition data automatically and/or autonomously based on a memory constraint associated with a resource such as a target device. Logic may identify a tag in the code to identify a task, wherein the task comprises at least one loop, the loop to process data elements in one or more arrays. Logic may automatically generate instructions to determine one or more partitions for the at least one loop to partition data elements, accessed by one or more memory access instructions for the one or more arrays within the at least one loop, based on a memory constraint, the memory constraint to identify an amount of memory available for allocation to process the task. Logic may determine one or more iteration space blocks for the parallel loops, determine memory windows for each block, copy data into and out of constrained memory, and transform array accesses.
    Type: Application
    Filed: May 7, 2018
    Publication date: February 7, 2019
    Applicant: INTEL CORPORATION
    Inventors: Rakesh Krishnaiyer, Konstantin Bobrovskii, Dmitry Budanov
  • CODING TOOLS FOR SUBJECTIVE QUALITY IMPROVEMENTS IN VIDEO CODECS
    Publication number: 20190045185
    Abstract: Coding tools are described for subjective quality improvements in video codecs. Some embodiments pertain to a method that includes receiving video frames, generating a segmentation map of a received video frame, determining features of a segment of the segmentation map, determining if the segment has a skip or a reference frame feature, and if the segment has one of a skip or a reference frame feature, then classifying the segment as an active segment and attaching an active segment identifier to the segment.
    Type: Application
    Filed: December 27, 2017
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventor: Fangwen Fu
  • Non-synchronized RF Ranging
    Publication number: 20190041508
    Abstract: Various systems and methods for determining a distance between a master device and a slave device based, at least in part, on a received signal strength and based, at least in part, on a time interval including generation of a master ranging symbol and detection of a slave ranging symbol.
    Type: Application
    Filed: January 12, 2018
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventors: Raghavendra R., RAGHAVENDRA BHAT, VISWANATH DIBBUR
  • METHOD AND SYSTEM OF REFLECTION SUPPRESSION FOR IMAGE PROCESSING
    Publication number: 20190042871
    Abstract: A system, article, and method of reflection suppression for image processing by detecting undesired reflected objects in an image.
    Type: Application
    Filed: March 5, 2018
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventor: Oleg Pogorelik
  • DEEP COMPRESSED NETWORK
    Publication number: 20190042926
    Abstract: An embodiment of a semiconductor package apparatus may include technology to apply a low rank factorization to a weight matrix of a decision network to determine a first weight matrix approximation, reshape the first weight matrix approximation into a second weight matrix approximation, and compress the decision network based on the second weight matrix approximation. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: May 11, 2018
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventors: Sara Baghsorkhi, Matthew Sotoudeh