Abstract: A light pattern projector with a pattern mask to spatially modulate an intensity of a wideband illumination source, such as an LED, and a projector lens to reimage the spatially modulated emission onto regions of a scene that is to be captured with an image sensor. The projector lens may comprise a microlens array (MLA) including a first lenslet to reimage the spatially modulated emission onto a first portion of a scene, and a second lenslet to reimage the spatially modulated emission onto a first portion of a scene. The MLA may have a fly's eye architecture with convex curvature over a diameter of the projector lens in addition to the lenslet curvature. The pattern mask may be an amplitude mask comprising a mask pattern of high and low amplitude transmittance regions. In the alternative, the pattern mask may be a phase mask, such as a refractive or diffractive mask.

Abstract: A phase change memory (PCM) cell can include a PCM layer. A first electrode and a second electrode disposed on opposite sides of the PCM layer. The first electrode, the second electrode, or both includes a metal ceramic composite material layer disposed between an upper barrier layer and a lower barrier layer and wherein the metal ceramic composite material layer provides a corresponding electrode with an electrical resistivity of from 10 mOhm-cm to 1000 mOhm-cm.

Abstract: Technologies are provided in embodiments including a memory element to store a payload indicating an action to be performed associated with a remote action request (RAR) and a remote action handler circuit to identify the action to be performed, where the action includes invalidating one or more entries of a translation lookaside buffer (TLB), determine that the logical processor entered an enclave mode during a prior epoch, perform one or more condition checks on control and state pages of the enclave mode, and based on results of the one or more condition checks, adjust one or more variables associated with the logical processor to simulate the logical processor re-entering the enclave mode. Specific embodiments include the remote action handler circuit to invalidate an entry of the TLB based, at least in part, on the results of the one or more condition checks.

Abstract: Systems, devices, and techniques related to selecting a key frame for burst image processing are discussed. Such techniques may include generating key frame scores for at least some frames of a multi-frame burst image capture such that the key frame scores include a combination of an image quality component, a shutter lag component, and a burst image processing latency component and selecting a frame having a maximum key frame score as the key frame.

Abstract: Particular embodiments described herein provide for a system for enabling the communication of a large message using multiple network interface controllers (NICs). The system can be configured to determine that a message to communicate to a receiver over a network is above a threshold, determine a plurality of NICs to be used to communicate the message, create a manifest that includes an identifier of each of the plurality of NICs, and communicate the manifest to the receiver using a multi-unit message. In an example, the multi-unit message is communicated using a PUT command and the receiver can analyze the manifest and use a GET command to pull the message from the plurality of NICs.

Abstract: An integrated circuit package may include one or more integrated circuit dies and reconfigurable constrained vapor bubble (CVB) heat pipe structures formed on the integrated circuit dies. The reconfigurable CVB heat pipe structures may be adjusted using micro-electro-mechanical systems (MEMS) switches. By turning on a MEMS switch, the corresponding heat pipe structure will exhibit a first heat transfer efficiency. By turning off a MEMS switch, the corresponding heat pipe structure will exhibit a second heat transfer efficiency that is less than the first heat transfer efficiency. The reconfigurable CVB heat pipe structures may be statically programmed and/or dynamically adjusted as hot spot locations within the integrated circuit package migrate over time.

Abstract: Techniques related to applying computer vision to decompressed video are discussed. Such techniques may include generating a region of interest in an individual video frame by translating spatial indicators of a first detected computer vision result from a reference video frame to the individual video frame and applying a greater threshold within the region of interest than outside of the region of interest for computer vision evaluation in the individual frame.

Abstract: In one example, a system for managing access to hardware components includes a processor to manage a transition of a component from a known trusted first state and a context of a first application to a known trusted second state and a context of a second application based on trusted meta-data. The processor can also prevent contamination across the known trusted state of each application based on the trusted meta-data associated with each application. Additionally, the processor can detect a change of a trust boundary from the first application to the second application, save the first state of the first application accessing the component, remove said first state from the component, initialize and load the second state of the second application accessing the component, and execute the second application via the component based on the second state.

Abstract: The present disclosure is directed to systems and methods for providing protection against replay attacks on memory, by refreshing or updating encryption keys. The disclosed replay protected computing system may employ encryption refresh of memory so that unauthorized copies of data are usable for a limited amount of time (e.g., 500 milliseconds or less). The replay protected computing system initially encrypts protected data prior to storage in memory. After a predetermined time or after a number of memory accesses have occurred, the replay protected computing system decrypts the data with the existing key and re-encrypts data with a new key. Unauthorized copies of data (such as those made by an adversary system/program) are not refreshed with subsequent new keys. When an adversary program attempts to use the unauthorized copies of data, the unauthorized copies of data are decrypted with the incorrect keys, which renders the decrypted data unintelligible.

Abstract: Particular embodiments described herein provide for an electronic device that can be configured to help with the identification of a no-operation (NOP) sled attack identify. The system can be configured to receive an instruction, increment a value in a total instruction counter, increment a value in a branch instruction counter when the instruction is a branch instruction, increment a value in a memory instruction counter when the instruction is a memory instruction, create a ratio based on the value in the total instruction counter and the value in the branch instruction counter or the value in the memory instruction counter, and trigger an alert when the ratio satisfies a threshold. The ratio can indicate the presence of a NOP sled attack and the alert can be an interrupt that stops execution of the NOP sled.

Abstract: Techniques related to generating a virtual view from multi-view images for presentation to a viewer are discussed. Such techniques include determining, based on a viewer position relative to a display region, first and second crop positions of planar image and cropping the planar image to a cropped planar image to fill the display region using the first and second crop positions such that the first and second crop positions define an asymmetric frustum between the cropped planar image and a virtual window corresponding to the display region.

Abstract: Systems, devices, and techniques related to matching features between a dynamic vision sensor and one or both of a dynamic projector or another dynamic vision sensor are discussed. Such techniques include casting a light pattern with projected features having differing temporal characteristics onto a scene and determining the correspondence(s) based on matching changes in detected luminance and temporal characteristics of the projected features.

Abstract: There is disclosed in one example a computing apparatus, including: a hardware platform; a network interface to communicatively couple to a bus lacking native support for authentication; and an anomaly detection engine to operate on the hardware platform and configured to: receive a first data stream across a first time; symbolize and approximate the first data stream, including computing a first window sum; receive a second data stream across a second time substantially equal in length to the first time, the second data stream including data across the plurality of dimensions from the first data stream; symbolize and approximate the second data stream, including computing a second window sum; compute a difference between the first window sum and the second window sum; determine that difference exceeds a threshold and that the correlation across the plurality of dimensions is broken; and flag a potential anomaly.

Abstract: Technology for a memory device is described. The memory device can include an array of memory cells and a memory controller. The memory controller can receive a request to program a memory cell within the array of memory cells. The memory controller can select a current magnitude and a duration of the current magnitude for a programming set pulse based on a polarity of access for the memory cell, a number of prior write cycles for the memory cell, and electrical distances between the memory cell and wordline/bitline decoders within the array of memory cells. The memory controller can initiate, in response to the request, the programming set pulse to program the memory cell within the array of memory cells. The selected current magnitude and the selected duration of the current magnitude can be applied during the programming set pulse.

Abstract: Reduction of program disturb degradation in a flash memory cell array is facilitated by selectively switching wordline voltage levels in a sequence that reduces the likelihood of trapping electrons in memory cell channels. During a program verify operation for a memory cell in a memory cell string, a flash memory system switches wordline voltage levels from high-to-low for interface wordlines, prior to switching wordline voltages from high-to-low for other wordlines in a memory cell string. Selectively switching wordlines in a sequence in the memory cell string enables electrons to migrate to ground or to a source voltage through upper and lower select gates.

Abstract: Embodiments may relate to a polymer optical coupler. The polymer optical coupler may include a first portion at least partially coupled to a face of a silicon waveguide. The polymer optical coupler may further include a second portion of the polymer optical coupler that is adjacent to the first portion and which may have a width that is less than a width of the second portion opposite the first portion. Other embodiments may be described and/or claimed.

Abstract: The systems and methods disclosed herein provide an improved processor package to determine a connection type between the package and an external circuit and to optimize processor performance based on the connection type. As a non-limiting example, a processor package consistent with the present disclosure may include a central processing unit (CPU) die and a plurality of pins (including two connection detection pins) to connect the package to a motherboard. The CPU die may include connection determination logic and execution policy logic, implemented via processor code (“p-code”), as well as a more typical processor.

Abstract: A mechanism is described for facilitating automatic tuning of image signal processors using reference images in image processing environments, according to one embodiment. A method of embodiments, as described herein, includes one or more processors to: receive images associated with one or more scenes captured by one or more cameras; access tuning parameters associated with functionalities within an image signal processor (ISP) pipeline; generate reference images based on the tuning parameters, wherein a reference image is associated with an image for each functionality within the ISP pipeline; and automatically tune the ISP pipeline based on selection of one or more of the reference images for one or more of the images for one or more of the functionalities.

Abstract: Techniques related to video encoding are discussed that, for each block of input video, select an individual partitioning and coding mode selection technique from multiple such selection techniques. For a picture, the selection algorithm takes as input scores for individual blocks, costs of the various partitioning and coding mode selection techniques, and various detector outputs. The selection algorithm provides as output a partitioning and coding mode selection technique for each block in picture. The algorithms selection is such that the overall cost of the selected algorithms in the picture is as close as possible to a given picture budget. Furthermore, a partitioning and coding mode selection algorithms, binary depth partitioning (BDP), is discussed. For a block, BDP provides fast convergence to a partitioning and associated coding modes first evaluating intermediate partitioning options and converging on the final partitioning by evaluating either larger of smaller partitions.

Abstract: A transceiver circuit includes a clock management circuit that generates control signals indicating power state information for logic circuits. The clock management circuit changes the power state information indicated by the control signals based on a change in an indication of a power state that is generated by an external source and that is received in a data stream at the transceiver circuit or based on a change in an amount of data stored in an internal queue. The transceiver circuit also includes a dynamic clock control circuit that receives the control signals and that generates a clock signal that is provided to the logic circuits. The dynamic clock control circuit adjusts a frequency of the clock signal based on the control signals indicating a change in the power state information generated by the clock management circuit to adjust the power state of the logic circuits.