Abstract: A transistor device may include a first perovskite gate material, a first perovskite ferroelectric material on the first gate material, a first perovskite semiconductor material on the first ferroelectric material, a second perovskite ferroelectric material on the first semiconductor material, a second perovskite gate material on the second ferroelectric material, a third perovskite ferroelectric material on the second gate material, a second perovskite semiconductor material on the third ferroelectric material, a fourth perovskite ferroelectric material on the second semiconductor material, a third perovskite gate material on the fourth ferroelectric material, a first source/drain metal adjacent a first side of each of the first semiconductor material and the second semiconductor material, a second source/drain metal adjacent a second side opposite the first side of each of the first semiconductor material and the second semiconductor material, and dielectric materials between the source/drain metals and the

Abstract: An example of an integrated circuit may include a first execution cluster, a second execution cluster that is one or more of narrower and shallower as compared to the first execution cluster, and circuitry to selectively steer instructions to the first execution cluster and the second execution cluster based on branch misprediction information. Other embodiments are disclosed and claimed.

Abstract: A system and method for generating, from a permutation of a first input state, a first output state, a first rate and a first capacity, the first rate including a first portion of the first output state and the first capacity including a second portion of the first output state; storing the first output state; generating a first block of ciphertext data of a first packet from XORing the first rate and a first block of plaintext data of the first packet; generating a permutation of a value of the first block of ciphertext data of the first packet concatenated with the first capacity, and generating a second block of ciphertext data of the first packet from XOR of the permutation of the value of the first block of ciphertext data of the first packet concatenated with the first capacity.

Abstract: IC devices with angled interconnects are disclosed herein. An interconnect, specifically a trench or line interconnect, is referred to as an “angled interconnect” if the interconnect is neither perpendicular nor parallel to any edges of front or back faces of the support structure, or if the interconnect is not parallel or perpendicular to interconnect in another region of an interconnect layer. Angled interconnects may be used to decrease the area of pitch transition regions. Angled interconnects may also be used to decrease the area of pitch offset regions.

Abstract: Various arrangements for IC devices implementing memory with one access transistor for multiple capacitors are disclosed. An example IC device includes a memory array of M memory units, where each memory unit includes an access transistor and N capacitors coupled to the access transistor. A portion of the capacitors are formed in one or more layers above the access transistor, and a portion of the capacitors are formed in one or more layers below the access transistor. The capacitors in a particular memory unit may be coupled to a single via or to individual vias. In some embodiments, some of the vias are backside vias.

Abstract: A method comprises receiving, from a remote device, an audio/video input signal, identifying one or more objects in the audio/video input signal tagged as a sensitive object, evaluating a set of workload requirements for a set of processing workloads comprising portions of the audio/video input signal, selecting one or more heavy processing workloads in the set of processing workloads to send to a compute service provider, in response to a determination that the one or more heavy processing workloads comprises one or more objects tagged as a sensitive object, encrypting the one or more objects tagged as a sensitive object using a homomorphic encryption protocol to generate a first homomorphically encrypted string, and sending the first homomorphically encrypted string to the compute service provider via a privacy protected communication channel.

Abstract: An IC device includes a metal layer that includes staggered metal lines. The metal lines are in two or more levels along a direction. There may be one or more metal lines in each level. At least some of the metal lines are aligned along the direction so that widths of the metal lines may be maximized for a given total width of the metal layer. The alignment of the metal lines may be achieved through DSA of a diblock copolymer. The metal layer may be connected to vias in two or more levels. The vias may be also connected to another metal layer or a semiconductor device in a FEOL section of the IC device. A via and the metal line connected to the via may be formed through a same recess and deposition process to eliminate interface between the via and metal line.

Abstract: Technologies for a hybrid digital/analog processor for a quantum computer are disclosed. In the illustrative embodiment, a hybrid digital/analog processor may be able to process digital instructions as well as analog instructions. The digital instructions may be, e.g., read from or write to memory or registers, perform an arithmetic operation, perform a branch, etc. The analog instructions may be to, e.g., provide an analog voltage to a particular electrode of a qubit, provide an analog pulse to a qubit, measure a reflection of an analog signal from a qubit, etc. The integration of analog operations in the hybrid digital/analog processor can improve performance by, e.g., lowering latency and lowering power usage.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for intentional programming for heterogeneous systems. An example non-transitory computer readable storage medium includes instructions that, when executed, cause processor circuitry to at least identify a first code block having a first algorithmic purpose based on a second code block having a second algorithmic purpose, the second algorithmic purpose corresponding to the first algorithmic purpose, translate the first code block into executable domain specific language code, and output the executable domain specific language code.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for sparse tensor storage for neural network accelerators. An example apparatus includes sparsity map generating circuitry to generate a sparsity map corresponding to a tensor, the sparsity map to indicate whether a data point of the tensor is zero, static storage controlling circuitry to divide the tensor into one or more storage elements, and a compressor to perform a first compression of the one or more storage elements to generate one or more compressed storage elements, the first compression to remove zero points of the one or more storage elements based on the sparsity map and perform a second compression of the one or more compressed storage elements, the second compression to store the one or more compressed storage elements contiguously in memory.

Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to a substrate that includes a first region to be coupled with a die, and a second region separate and distinct from the first region that has a lower thermal conductivity than the first region, where the second region is to thermally insulate the first region when the die is coupled to the first region. The thermal insulation of the second region may be used during a TCB process to increase the quality of each of the interconnects of the die by promoting a higher temperature at the connection points to facilitate full melting of solder.

Abstract: Systems and methods of beamforming and improving mmWave communications for drones are described. Multiple RF chains are used to adapt the main beam to track changes without the use of pilot signals. To reduce interference, interfering signal power is eliminated by optimizing a non-Gaussian measure to extract the interferers. The AoA of signals from a target drone on neighbouring drones and location of the neighbouring drones and base stations are used to independently corroborate the location reported by the target drone. The base station provides additional synchronization signals below 6 GHz and restricts the search/measurement space in the vertical direction. The inherent sparse structure above 6 GHz is exploited by applying different beamformers on a sounding signal and estimating the AoA and impulse response. Variations of fully digital and hybrid beamforming architectures for multi-cell DL sync and CRS measurement are described.

Abstract: For example, an apparatus may be configured to generate, transmit, receive and/or process a frame including a multiple Basic Service Set Identifier (BSSID) element corresponding to a multiple BSSID set including a reporting AP, the BSSID element including one or more non-transmitted BSSID profile elements corresponding to one or more other APs belonging to the multiple BSSID set, wherein a non-transmitted BSSID profile element corresponding to an other AP includes one or more elements of information corresponding to the other AP, and a multi-link element, the multi-link element including one or more profile subelements for one or more reported APs of an other MLD including the other AP, respectively, wherein a profile subelement corresponding to a reported AP includes one or more elements of information corresponding to the reported AP.

Abstract: To address the issue of shrinking volume that can be allocated for electrical components, a system can use an interposer with a flexible portion. A first portion of the interposer can electrically connect to a top side of a motherboard. A flexible portion of the interposer, adjacent to the first portion, can wrap around an edge of the motherboard. A peripheral portion of the interposer, adjacent to the flexible portion, can electrically connect to a bottom side of the motherboard. The peripheral portion can be flexible or rigid. The interposer can define a cavity that extends through the first portion of the interposer. A chip package can electrically connect to the first portion of the interposer. The chip package can be coupled to at least one electrical component that extends into the cavity when the chip package is connected to the interposer.

Abstract: In one embodiment, a hinge apparatus includes two curved rack apparatuses, each curved rack apparatus defining an arcuate surface and an arcuate set of gear teeth concentric with the arcuate surface, where the radius of curvature of the arcuate set of gear teeth being non-uniform. The hinge apparatus further includes a gear assembly that includes a first gear, a second gear, a third gear coupling the first and second gears, a fourth gear coupling the first gear and the arcuate set of gear teeth of the first curved rack apparatus, and a fifth gear coupling the second gear and the arcuate set of gear teeth of the second curved rack apparatus.

Abstract: Techniques for memory tagging are disclosed. In the illustrative embodiment, 16 bits of a virtual memory address are used as memory tag bits. In a page table entry corresponding to the virtual memory address, page tag bits indicate which of the 16 bits of the virtual memory address are to be sent to the memory as memory tag bits when a memory operation is requested on the virtual memory address. The memory can then compare the memory tag bits sent with the physical memory address to memory tag bits stored on the memory that correspond to the physical memory address. If the memory tag bits match, then the operation is allowed to proceed.

Abstract: A data processing system includes technology for detecting and tolerating faults. The data processing system comprises an electronic control unit (ECU) with a processing core and a fault-tolerant elliptic curve digital signature algorithm (ECDSA) engine. The fault-tolerant ECDSA engine comprises multiple verification state machines (VSMs). The data processing system also comprises nonvolatile storage in communication with the processing core and ECU software in the nonvolatile storage. The ECU software, when executed, enables the data processing system to operate as a node in a distributed data processing system, including receiving digitally signed messages from other nodes in the distributed data processing system. The ECU further comprises a known-answer built-in self-test unit (KA-BISTU). Also, the ECU software comprises fault-tolerant ECDSA engine (FTEE) management software which, when executed by the processing core, utilizes the KA-BISTU to periodically test the fault-tolerant ECDSA engine for faults.

Abstract: An apparatus to facilitate disaggregated computing for a distributed confidential computing environment is disclosed. The apparatus includes a source remote direct memory access (RDMA) network interface controller (RNIC); a queue to store a data entry corresponding to an RDMA request between the source RNIC and a sink RNIC; a data buffer to store data for an RDMA transfer corresponding to the RDMA request, the RDMA transfer between the source RNIC and the sink RNIC; and a trusted execution environment (TEE) comprising an authentication tag controller to: initialize a first authentication tag calculated using a first key known between a source consumer generating the RDMA request and the source RNIC; associate the first authentication tag with the data entry as integrity verification; initialize a second authentication tag calculated using a second key; and associate the second authentication tag with the data buffer as integrity verification for the data buffer.

Abstract: Three components are used to adjust the CPU peak power based on the USB TYPE-C device states. These components include operating system (OS) Peak Power Manager, USB TYPE-C Connector Manager, and USB TYPE-C Protocol Device Driver. The USB TYPE-C Connector Manager sends a synchronous request to the OS Peak Power Manager when a USB TYPE-C power sink device is attached or detached, and the USB TYPE-C Protocol Device Driver sends a synchronous request to the Peak Power Manager when the power sink transitions device state. The Peak Power Manager takes power budget from the CPU when the USB TYPE-C connector is attached to a power sink and is active (e.g., high power device state), and gives back the power budget to the CPU for performance when the USB TYPE-C connector is either detached or the attached and power sink device is idle (lowest device state).

Abstract: An example system for lightweight view dependent rendering is described herein. An example mobile device includes a display, instructions, and processor circuitry to execute instructions to extract a moving region within a first set of frames of volumetric video content captured by a plurality of real-world cameras facing a scene at different angles. The processor circuitry to generate a first billboard based on a cropped area of the frames in the first set of frames, the cropped area corresponding to the first moving region. The processor circuitry to, in response to user selection of a first view of the scene, cause presentation of the first billboard on the display. The processor circuitry to, in response to a change from the first view to a second view of the scene, cause a second billboard to replace the first billboard on the display.