Abstract: An apparatus is described. The apparatus includes a long short term memory (LSTM) circuit having a multiply accumulate circuit (MAC). The MAC circuit has circuitry to rely on a stored product term rather than explicitly perform a multiplication operation to determine the product term if an accumulation of differences between consecutive, preceding input values has not reached a threshold.

Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.

Abstract: Integrated circuit structures including device terminal interconnect pillar structures, and fabrication techniques to form such structures. Following embodiments herein, a small transistor terminal interconnect footprint may be achieved by patterning recesses in a gate interconnect material and/or a source or drain interconnect material. A dielectric deposited over the gate interconnect material and/or source or drain interconnect material may be planarized to expose portions of the gate interconnect material and/or drain interconnect material that were protected from the recess patterning. An upper level interconnect structure, such as a conductive line or via, may contact the exposed portion of the gate and/or source or drain interconnect material.

Abstract: Various embodiments are generally directed to an apparatus, system, and other techniques for dynamic and intelligent deployment of a neural network or any inference model on a hardware executor or a combination of hardware executors. Computational costs for one or more operations involved in executing the neural network or inference model may be determined. Based on the computational costs, an optimal distribution of the computational workload involved in running the one or more operations among multiple hardware executors may be determined.

Abstract: Embodiments disclosed herein include electronic packages with a ground plate embedded in the solder resist that extends over signal traces. In an embodiment, the electronic package comprises a substrate layer, a trace over the substrate layer, and a first pad over the substrate layer. In an embodiment, a solder resist is disposed over the trace and the first pad. In an embodiment a trench is formed into the solder resist, and the trench extends over the trace. In an embodiment, a conductive plate is disposed in the trench, and is electrically coupled to the first pad by a via that extends from a bottom surface of the trench through the solder resist.

Abstract: An apparatus and method for efficiently improving virtual/real interactions in augmented reality. For example, one embodiment of a method comprises: capturing a raw image including depth data; identifying one or more regions of interest based on a detected spatial proximity of one or more virtual objects and one or more real objects; generating a super-resolution map of the one or more regions of interest using machine-learning techniques or results thereof; detecting interactions between the virtual objects and the real objects using the super-resolution map; and performing one or more graphics processing or general purpose processing operations based on the detected interactions.

Abstract: An embodiment of a novel memory circuit is described that improves post aging performance of a shared VCC node with a write pre-charge on the supply line. A write pre-charge PMOS device is added to the shared VCC node in some embodiments. The write pre-charge circuit helps insure that the shared VCC node has a healthy voltage value at the beginning of a write phase and also enables the memory circuit to recover the shared VCC value after the write phase (e.g., immediately following), enabling a read operation after a write operation for a same register file entry or adjacent entries (e.g., entries connected to the same shared VCC node). Other embodiments are disclosed and claimed.

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a substrate, and a first transistor of a first conductivity type over the substrate. In an embodiment, the first transistor comprises a first semiconductor channel, and a first gate electrode around the first semiconductor channel. In an embodiment, the semiconductor device further comprises a second transistor of a second conductivity type above the first transistor. The second transistor comprises a second semiconductor channel, and a second gate electrode around the second semiconductor channel. In an embodiment, the second gate electrode and the first gate electrode comprise different materials.

Abstract: Various systems and methods for implementing random access channel security are described herein. An apparatus for a base station includes: receiver circuitry to receive at the base station, a signal from a user equipment (UE) transmitter to access resources of the base station; statistics circuitry to calculate high-order statistics on the signal to produce an identification indication; a memory device to store the high-order statistics and the identification indication; and processing circuitry to: associate the identification indication with the UE transmitter; use the identification indication to determine that multiple failures of a random access channel (RACH) process have occurred from the UE transmitter; and restrict later attempts by the UE transmitter to perform RACH processes with the base station.

Abstract: A system includes an electronic display to display a virtual keyboard and a processor communicatively coupled to the electronic display. In some embodiments, the virtual keyboard includes a plurality of keys. In certain embodiments, the electronic display receives a first string of erased characters and a second string of replacement characters. In certain embodiments, the processor compares the first string and the second string to determine a difference at corresponding character locations of the first string and the second string. In some embodiments, the processor increments a counter based on the comparison, the counter corresponding to a first character of the first string and a second character of the second string. In certain embodiments, the processor adjusts at least one of the plurality of keys of the virtual keyboard in response to the counter meeting a threshold.

Abstract: Examples relate to a transmission apparatus, transmission device, transmission method and computer program for a source device, and to a reception apparatus, reception device, reception method and computer program for a destination device. The transmission apparatus is suitable for generating a header of a transmission frame to be transmitted downstream from a source device to a plurality of destination devices via a point to multipoint communication network. The transmission apparatus comprises processing circuitry configured to generate the header based on a plurality data units to be transmitted to the destination devices. Each data unit is designated to be transmitted to one of the destination devices. The processing circuitry wherein the header is generated such, that the header comprises, for each destination device, information on a presence of data for the destination device in the transmission frame associated with the header.

Abstract: A method comprises generating a first set of hardware performance counter (HPC) events that is ranked based on an ability of an individual HPC event to profile a malware class, generating a second set of HPC event combinations that is ranked based on an ability of a set of at least two joint HPC events to profile a malware class, generating a third set of extended HPC event combinations, profiling one or more malware events and one or more benign applications to obtain a detection accuracy parameter for each malware event, applying a machine learning model to rank the third set of HPC event combinations based on malware detection accuracy, and applying a genetic algorithm to the third set of HPC event combinations to identify a subset of the third set of extended combinations of HPC events to be used for malware detection and classification.

Abstract: Various embodiments herein define a performance data and measurement job creation solutions for advanced networks including network slicing, based on a service-based framework. The embodiments allow different kinds of consumers to flexibly use performance management services and performance data services, to collect real-time performance data and/or periodical performance data.

Abstract: An interface couples a controller to a physical layer (PHY) block, where the interface includes a set of data pins comprising transmit data pins to send data to the PHY block and receive data pins to receive data from the PHY block. The interface further includes a particular set of pins to implement a message bus interface, where the controller is to send a write command to the PHY block over the message bus interface to write a value to at least one particular bit of a PHY message bus register, bits of the PHY message bus register are mapped to a set of control and status signals, and the particular bit is mapped to a recalibration request signal to request that the PHY block perform a recalibration.

Abstract: A method comprises fetching, by fetch circuitry, an encoded butterfly instruction comprising an opcode, a first source identifier, a second source identifier, a third source identifier, and two destination identifiers, decoding, by decode circuitry, the decoded butterfly instruction to generate a decoded butterfly instruction, and executing, by execution circuitry, the decoded butterfly instruction to retrieve operands representing a first input polynomial-coefficient from the first source, a second input polynomial-coefficient from the second source, and a primitive nth root of unity from the third source, perform, in an atomic fashion, a butterfly operation to generate a first output polynomial-coefficient and a second output polynomial-coefficient, and store the first output coefficient and the second output coefficient in a register file accessible to the execution circuitry.

Abstract: Examples described herein relate to during a boot of a power supply unit (PSU) connected to a computer platform, circuitry to receive a firmware identifier and manufacturer identifier associated with the PSU and determine whether the PSU is approved to utilize. In some examples, based on, at least, authentication of the firmware identifier and manufacturer identifier of the PSU, the circuitry is to permit access to data and/or power from the PSU. In some examples, based on, at least, failure to authenticate the firmware identifier or manufacturer identifier of the PSU, the circuitry is to deny access to data and/or power from the PSU.

Abstract: Embodiments for automatically tuning heterogenous wireless networks are disclosed herein. In one example, performance data is received for multiple wireless networks. The wireless networks are based on multiple wireless technologies, and the performance data is based on multiple layers of the protocol stacks of the wireless technologies. The performance data is used to determine one or more configuration settings to adjust for one or more of the wireless networks. The determined configuration setting(s) are then adjusted.

Abstract: A shared memory controller receives, from a computing node, a request associated with a memory transaction involving a particular line in a memory pool. The request includes a node address according to an address map of the computing node. An address translation structure is used to translate the first address into a corresponding second address according to a global address map for the memory pool, and the shared memory controller determines that a particular one of a plurality of shared memory controllers is associated with the second address in the global address map and causes the particular shared memory controller to handle the request.

Abstract: Embodiments for allocating shared resources are disclosed. In an embodiment, an apparatus includes a core and a hardware rate selector. The hardware rate selector is to, in response to a first indication that demand for memory bandwidth from the core has reached a threshold value, determine a delay value to be used to limit allocation of memory bandwidth to the core. The hardware rate selector includes a controller having a first counter to count a second indication of demand for memory bandwidth from the first core and a second counter to count expirations of time windows. The first indication is based on a difference between the first counter value and the second counter value.