Abstract: Composite integrated circuit (IC) device structures that include two components coupled through hybrid bonded interconnect structure. The two components may be two different monolithic IC structures (e.g., chips) that are bonded over a substantially planar dielectric and metallization layer. A surface of a metallization feature may be augmented with supplemental metal, for example to at least partially backfill a recess in a surface of the metallization feature as left by a planarization process. In some exemplary embodiments, supplemental metal is deposited selectively onto a metallization feature through an autocatalytic (electroless) metal deposition process. A surface of a dielectric material surrounding a metallization feature may also be recessed, for example to at least partially neutralize a recess in an adjacent metallization feature, for example resulting from a planarization process.

Abstract: A transistor includes a semiconductor body including a material such as an amorphous or polycrystalline material, for example and a gate stack on a first portion of the body. The gate stack includes a gate dielectric on the body, and a gate electrode on the gate dielectric. The transistor further includes a first metallization structure on a second portion of the body and a third metallization structure on a third portion of the body, opposite to the second portion. The transistor further includes a ferroelectric material on at least a fourth portion of the body, where the ferroelectric material is between the gate stack and the first or second metallization structure.

Abstract: An apparatus comprising: a model to generate adjusted tuning parameters of a thread scheduling policy based on a tradeoff indication value of a target system; and a workload monitor to: execute a workload based on the thread scheduling policy; obtain a performance score and a power score from the target system based on execution of the workload, the performance score and the power score corresponding to a tradeoff indication value; compare the tradeoff indication value to a criterion; and based on the comparison, initiate the model to re-adjust the adjusted tuning parameters.

Abstract: A Bluetooth receiver is provided. The Bluetooth receiver comprises processing circuitry configured to receive a receive signal and to determine receive symbols based on the receive signal. The Bluetooth receiver further comprises control circuitry configured to determine a frequency offset and/or a modulation index of the receive signal based on the receive signal. The control circuitry is additionally configured to control an operation mode of the processing circuitry based on the determined frequency offset and/or the modulation index of the receive signal.

Abstract: For example, a Next Generation Vehicular (NGV) wireless communication station (STA) may be configured to generate an NGV Physical Layer (PHY) Protocol Data Unit (PPDU) including an NGV preamble, the NGV preamble comprising a non High-Throughput (non-HT) Short Training Field (L-STF), a non-HT Long Training Field (L-LTF) after the L-STF, a non-HT Signal (L-SIG) field after the L-LTF, a Repeated L-SIG (RL-SIG) field after the L-SIG field, and an NGV Signal (NGV-SIG) field after the RL-SIG field, the NGV-SIG field including a version field configured to identify a version of the NGV PPDU; and to transmit the NGV PPDU over an NGV channel in an NGV wireless communication frequency band; and a memory to store information processed by the processor.

Abstract: Embodiments of systems, apparatuses, and methods for fused multiple add. In some embodiments, a decoder decodes a single instruction having an opcode, a destination field representing a destination operand, and fields for a first, second, and third packed data source operand, wherein packed data elements of the first and second packed data source operand are of a first, different size than a second size of packed data elements of the third packed data operand.

Abstract: Programming a multilevel cell (MLC) nonvolatile (NV) media can be performed with internal buffer reuse to reduce the need for external buffering. The internal buffer is on the same die as the NV media to be programmed, along with a volatile memory to store data to program. The internal buffer is to read and program data for the NV media. Programming of the NV media includes staging first partial pages in the buffer for program, reading second partial pages from the NV media to the volatile memory, storing second partial pages in the buffer, and programming the NV media with the first partial pages and the second partial pages.

Abstract: Systems, apparatuses and methods may provide for technology that decodes data via an instruction that indicates a number of rulebooks to be processed, an input feature size, an output feature size, and a plurality of feature map base addresses, rearranges spatially distributed voxel output feature maps in the decoded data based on weight planes, and performs a channel-wise multiply-accumulate (MAC) operation on the rearranged spatially distributed voxel output feature maps to obtain an output, wherein the channel-wise MAC operation is performed as partial accumulations by a plurality of processing elements.

Abstract: Systems and methods of supporting RACH optimization and monitoring of UP packet delay performance are described. During RACH optimization, a NF provisioning MnS with modify MOIAttributes operation to configure targets for RACH optimization and a NF provisioning MnS with modifyMOIAttributes operation are separately consumed to enable a RACH optimization function for a NR cell. After this, a performance assurance MnS with notifyFileReady or reportStreamData operation is consumed to collect RACH optimization-related measurements for the NR cell and RACH performance data of the RACH optimization-related measurements analyzed to evaluate RACH optimization performance for the NR cell. During monitoring of UP packet delay performance, raw performance measurements related to UP packet delay based on at least one of NG-RAN measurement results or time stamps in GTP packets are obtained from a NG-RAN or UPF, UP packet delay performance measurements are generated.

Abstract: Disclosed herein are integrated circuit (IC) components with dummy structures, as well as related methods and devices. For example, in some embodiments, an IC component may include a dummy structure in a metallization stack. The dummy structure may include a dummy material having a higher Young's modulus than an interlayer dielectric of the metallization stack.

Abstract: Embodiments disclosed herein include transistors and methods of forming such transistors. In an embodiment, the transistor may comprise a semiconductor channel with a first surface and a second surface opposite the first surface. In an embodiment, a source electrode may contact the first surface of the semiconductor channel and a drain electrode may contact the first surface of the semiconductor channel. In an embodiment, a gate dielectric may be over the second surface of the semiconductor channel and a gate electrode may be separated from the semiconductor channel by the gate dielectric. In an embodiment, an isolation trench may be adjacent to the semiconductor channel. In an embodiment, the isolation trench comprises a spacer lining the surface of the isolation trench, and an isolation fill material.

Abstract: Technologies for cryptographic separation of MMIO operations with an accelerator device include a computing device having a processor and an accelerator. The processor establishes a trusted execution environment. The accelerator determines, based on a target memory address, a first memory address range associated with the memory-mapped I/O transaction, generates a second authentication tag using a first cryptographic key from a set of cryptographic keys, wherein the first key is uniquely associated with the first memory address range. An accelerator validator determines whether the first authentication tag matches the second authentication tag, and a memory mapper commits the memory-mapped I/O transaction in response to a determination that the first authentication tag matches the second authentication tag. Other embodiments are described and claimed.

Abstract: An integrated circuit package is disclosed. The integrated circuit package comprises a first integrated circuit die and a second integrated circuit die. The integrated circuit package further includes a substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the substrate. The substrate includes an interconnect bridge embedded within the substrate, wherein the interconnect bridge includes at least one metal trace component, wherein the metal trace component includes rounded corners on a bottom portion of the metal trace component.

Abstract: Methods and apparatus to operate closed-lid portable computers are disclosed. An example portable compute device includes: a microphone; a speaker; a first camera to face a first direction; and a second camera to face a second direction, the second direction opposite the first direction. The compute device further includes communications circuitry; a first display; a second display separate from the first display; and a hinge to enable the first display to rotate relative to the second display between an open position and a closed position. At least a portion of the second display is capable of being visible when the first display is rotated about the hinge to the closed position. The portion of the second display is multiple times longer in a third direction than in a fourth direction perpendicular to the third direction, the third direction extending parallel to an axis of rotation of the hinge.

Abstract: A memory controller is to store a unique tag at the mid-point address within each of allocated memory portions. In addition to the tag data, additional metadata may be stored at the mid-point address of the memory allocation. For each memory access operation, an encoded pointer contains information indicative of a size of the memory allocation as well as its own tag data. The processor circuitry compares the tag data included in the encoded pointer with the tag data stored in the memory allocation. If the tag data included in the encoded pointer matches the tag data stored in the memory allocation, the memory operation proceeds. If the tag data included in the encoded pointer fails to match the tag data stored in the memory allocation, an error or exception is generated.

Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

Abstract: Various embodiments herein provide techniques for wireless communication on New Radio unlicensed (NR-U) spectrum. For example, embodiments include techniques for a new listen-before-talk type and associated measurement window. Additionally, embodiments include techniques for determination of a cyclic prefix (CP) extension for an uplink transmission, such as a configured grant transmission or a dynamically scheduled transmission. Other embodiments may be described and claimed.

Abstract: In one embodiment, a processor includes: a plurality of cores; a first storage to store parameter information for a voltage regulator to couple to the processor via a voltage regulator interface; and a power controller to control power consumption of the processor. The power controller may determine a performance state for one or more cores of the processor and include a hardware logic to generate a message for the voltage regulator based at least in part on the parameter information, where this message is to cause the voltage regulator to output a voltage to enable the one or more cores to operate at the performance state. Other embodiments are described and claimed.

Abstract: Apparatus and method for grouping rays based on quantized ray directions. For example, one embodiment of an apparatus comprises: An apparatus comprising: a ray generator to generate a plurality of rays; ray direction evaluation circuitry/logic to generate approximate ray direction data for each of the plurality of rays; ray sorting circuitry/logic to sort the rays into a plurality of ray queues based, at least in part, on the approximate ray direction data.

Abstract: A die interconnect substrate comprises a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate comprises a multilayer substrate structure comprising a substrate interconnect. The bridge die is embedded in the multilayer substrate structure. The substrate interconnect extends from a level above the bridge die to a level below the bridge die. The multilayer substrate structure further comprises an electrically insulating layer comprising a first electrically insulating material. The multilayer substrate structure further comprises an electrically insulating filler structure located laterally between the bridge die and the electrically insulating layer, wherein the electrically insulating filler structure comprises a second electrically insulating material different from the first electrically insulating material.