Patents Assigned to Intel Corporations
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Patent number: 11234204Abstract: Systems, apparatuses, methods, and computer-readable media, are provided for selecting edge or central servers for serving client systems based on network events monitored by one or more network elements. Embodiments may be relevant to multi-access edge computing (MEC) and Automotive Edge Computing Consorium (AECC) technologies. Other embodiments may be described and/or claimed.Type: GrantFiled: February 10, 2020Date of Patent: January 25, 2022Assignee: Intel CorporationInventors: Zongrui Ding, Qian Li, Xiaopeng Tong, Leifeng Ruan
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Patent number: 11232948Abstract: The present disclosure provides systems and methods for a layered substrate. A layered substrate may include a core comprising graphite. The layered substrate may also include a coating layer comprising a coating material that surrounds the core, wherein the coating material has a melting point that is greater than a melting point of silicon.Type: GrantFiled: April 1, 2016Date of Patent: January 25, 2022Assignee: Intel CorporationInventors: Glenn A. Glass, Anand S. Murthy
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Patent number: 11233712Abstract: Technologies for connecting data cables in a data center are disclosed. In the illustrative embodiment, racks of the data center are grouped into different zones based on the distance from the racks in a given zone to a network switch. All of the racks in a given zone are connected to the network switch using data cables of the same length. In some embodiments, certain physical resources such as storage may be placed in racks that are in zones closer to the network switch and therefore use shorter data cables with lower latency. An orchestrator server may, in some embodiments, schedule workloads or create virtual servers based on the different zones and corresponding latency of different physical resources.Type: GrantFiled: December 30, 2016Date of Patent: January 25, 2022Assignee: Intel CorporationInventors: Matthew J. Adiletta, Aaron Gorius, Myles Wilde, Michael T. Crocker
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Patent number: 11233053Abstract: A device including a III-N material is described. In an example, the device has a terminal structure with a central body and a first plurality of fins, and a second plurality of fins, opposite the first plurality of fins. A polarization charge inducing layer including a III-N material in the terminal structure. A gate electrode is disposed above and on a portion of the polarization charge inducing layer. A source structure is on the polarization charge inducing layer and on sidewalls of the first plurality of fins. A drain structure is on the polarization charge inducing layer and on sidewalls of the second plurality of fins. The device further includes a source structure and a drain structure on opposite sides of the gate electrode and a source contact on the source structure and a drain contact on the drain structure.Type: GrantFiled: September 29, 2017Date of Patent: January 25, 2022Assignee: Intel CorporationInventors: Marko Radosavljevic, Han Wui Then, Sansaptak Dasgupta
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Patent number: 11231731Abstract: In one embodiment, a processor includes a minimum energy point (MEP) controller to: generate a change in thermal tracking information, based at least in part on prior and current thermal information; generate a change in activity tracking information, based at least in part on prior activity information and current activity information; and determine a MEP performance state based at least in part on the change in thermal tracking information and the change in activity tracking information. Other embodiments are described and claimed.Type: GrantFiled: June 28, 2019Date of Patent: January 25, 2022Assignee: Intel CorporationInventors: Sriram R. Vangal, Jayanth Mallanayakanahalli Devaraju, Vivek De, Robert Milstrey, Stephen H. Gunther
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Patent number: 11232536Abstract: An apparatus to facilitate data prefetching is disclosed. The apparatus includes a memory, one or more execution units (EUs) to execute a plurality of processing threads and prefetch logic to prefetch pages of data from the memory to assist in the execution of the plurality of processing threads.Type: GrantFiled: February 14, 2020Date of Patent: January 25, 2022Assignee: INTEL CORPORATIONInventors: Adam T. Lake, Guei-Yuan Lueh, Balaji Vembu, Murali Ramadoss, Prasoonkumar Surti, Abhishek R. Appu, Altug Koker, Subramaniam M. Maiyuran, Eric C. Samson, David J. Cowperthwaite, Zhi Wang, Kun Tian, David Puffer, Brian T. Lewis
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Patent number: 11233148Abstract: Integrated circuit transistor structures are disclosed that reduce band-to-band tunneling between the channel region and the source/drain region of the transistor, without adversely increasing the extrinsic resistance of the device. In an example embodiment, the structure includes one or more spacer configured to separate the source and/or drain from the channel region. The spacer(s) regions comprise a semiconductor material that provides a relatively high conduction band offset (CBO) and a relatively low valence band offset (VBO) for PMOS devices, and a relatively high VBO and a relatively low CBO for NMOS devices. In some cases, the spacer includes silicon, germanium, and carbon (e.g., for devices having germanium channel). The proportions may be at least 10% silicon by atomic percentage, at least 85% germanium by atomic percentage, and at least 1% carbon by atomic percentage. Other embodiments are implemented with III-V materials.Type: GrantFiled: November 6, 2017Date of Patent: January 25, 2022Assignee: Intel CorporationInventors: Benjamin Chu-Kung, Jack T. Kavalieros, Seung Hoon Sung, Siddharth Chouksey, Harold W. Kennel, Dipanjan Basu, Ashish Agrawal, Glenn A. Glass, Tahir Ghani, Anand S. Murthy
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Patent number: 11233018Abstract: Wireless modules having a semiconductor package attached to an antenna package is disclosed. The semiconductor package may house one or more electronic components as a single die package and/or a system in a package (SiP) implementation. The antenna package may be communicatively coupled to the semiconductor package using by one or more coupling pads. The antenna package may further have one or more radiating elements for transmitting and or receiving wireless signals. The antenna package and the semiconductor package may have dissimilar number of interconnect layers and/or dissimilar materials of construct.Type: GrantFiled: February 12, 2020Date of Patent: January 25, 2022Assignee: INTEL CORPORATIONInventors: Sidharth Dalmia, Ana M. Yepes, Pouya Talebbeydokhti, Miroslav Baryakh, Omer Asaf
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Patent number: 11233152Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.Type: GrantFiled: June 25, 2018Date of Patent: January 25, 2022Assignee: Intel CorporationInventors: Biswajeet Guha, William Hsu, Leonard P. Guler, Dax M. Crum, Tahir Ghani
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Patent number: 11231781Abstract: Example haptic gloves for virtual reality systems and related methods are disclosed herein. An example apparatus disclosed herein includes a glove to be worn on a hand of a user, an ultrasonic array disposed on an inner surface of the glove, and a control unit to activate the ultrasonic array device to generate haptic feedback on the hand of the user.Type: GrantFiled: August 3, 2017Date of Patent: January 25, 2022Assignee: Intel CorporationInventors: Yuan Xiong, Feiyue Zhai, Buddy Cao, Wenlong Yang
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Patent number: 11234129Abstract: This disclosure describes systems, methods, and devices related to an invalid location measurement report (LMR) indication. A device may identify a first null data packet (NDP) received from a first station device during, wherein the first NDP is used for channel sounding. The device may perform a time of arrival (ToA) calculation based on the NDP. The device may determine an invalid indication associated with the first NDP based on the ToA calculation. The device may generate an LMR comprising of the invalid measurement indication. The device may cause to send the LMR to the first device.Type: GrantFiled: December 26, 2018Date of Patent: January 25, 2022Assignee: Intel CorporationInventors: Feng Jiang, Qinghua Li, Jonathan Segev, Assaf Gurevitz, Danny Alexander, Xiaogang Chen
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Patent number: 11231937Abstract: A method and system method for communication port management in a device. The method including enabling a set of communication ports in response to power up of the device, detecting connection at a port in the set of communication ports prior to operating system boot of the device, and connecting an external device to an operational component of the device in response to the connection at the port.Type: GrantFiled: October 24, 2017Date of Patent: January 25, 2022Assignee: Intel CorporationInventor: Choon Gun Por
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Patent number: 11231761Abstract: Power monitoring circuitry is provided to monitor an input system power profile of processing tasks executing on a processing platform. An input is provided to receive from the processing platform, a processing system signal indicating a power being consumed by the processing platform. A counter is provided to store a count value corresponding to an accumulated number or amount of times that a warning threshold condition associated with a warning threshold value is satisfied by the received processing system signal in a count-accumulation time interval. The count value is supplied to a power control circuit of the processing platform via a bus in response to a read request from the power control circuit, the power control circuit being responsive to the count value to control a performance level of the processing platform.Type: GrantFiled: September 29, 2017Date of Patent: January 25, 2022Assignee: Intel CorporationInventors: Philip Lehwalder, Robert Santucci, Tod Schiff
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Patent number: 11234343Abstract: An integrated circuit structure may be formed having a first integrated circuit device, a second integrated circuit device electrically coupled to the first integrated circuit device, and at least one unidirectional heat transfer device between the first integrated circuit device and the second integrated circuit device. In one embodiment, the unidirectional heat transfer device may be oriented such that it has a higher conductivity in the direction of heat transfer from the first integrated circuit device to the second integrated circuit device than it does in the opposite direction. When the temperature of the second integrated circuit device rises above the temperature of the first integrated circuit device, the unidirectional heat transfer device will act as a thermal insulator, and when the temperature of the first integrated circuit device rises above the temperature of the second integrated circuit device, the unidirectional heat transfer device will act as a thermal conductor.Type: GrantFiled: May 3, 2018Date of Patent: January 25, 2022Assignee: Intel CorporationInventors: Feras Eid, Adel Elsherbini, Johanna Swan
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Patent number: 11232531Abstract: Various embodiments enable loop processing in a command processing block of the graphics hardware. Such hardware may include a processor including a command buffer, and a graphics command parser. The graphics command parser to load graphics commands from the command buffer, parse a first graphics command, store a loop count value associated with the first graphics command, parse a second graphics command and store a loop wrap address based on the second graphics command. The graphics command parser may execute a command sequence identified by the second graphics command, parse a third graphics command, the third graphics command identifying an end of the command sequence, set a new loop count value, and iteratively execute the command sequence using the loop wrap address based on the new loop count value.Type: GrantFiled: August 29, 2017Date of Patent: January 25, 2022Assignee: INTEL CORPORATIONInventors: Hema Chand Nalluri, Balaji Vembu, Peter Doyle, Michael Apodaca
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Patent number: 11233015Abstract: Device package and method of forming a device package are described. The device package has a substrate with dies disposed on the substrate. Each die has a bottom surface that is electrically coupled to the substrate and a top surface. The device package further includes a plurality of stiffeners disposed directly on the substrate. The stiffeners may be directly attached to a top surface of the substrate without an adhesive layer. The device package may include stiffeners with one or more different sizes and shapes, including at least one of a rectangular stiffener, a picture frame stiffener, a L-shaped stiffener, a H-shaped stiffener, and a round pillar stiffener. The device package may have the stiffeners disposed on the top surface of the substrate using a cold spray process. The device package may also include a mold layer formed around and over the dies, the stiffeners, and the substrate.Type: GrantFiled: September 30, 2017Date of Patent: January 25, 2022Assignee: Intel CorporationInventor: Feras Eid
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Patent number: 11232058Abstract: Methods and apparatuses associated with a secure stream protocol for a serial interconnect are disclosed herein. In embodiments, an apparatus comprises a transmitter and a receiver. The transmitter and receiver are configured to transmit and receive transaction layer data packets through a link, the transaction layer data packets including indicators associated with transmission of order set transmitted after a predetermined number of data blocks, when the transmission is during a header suppression mode. Additional features and other embodiments are also disclosed.Type: GrantFiled: August 29, 2019Date of Patent: January 25, 2022Assignee: Intel CorporationInventors: Michelle Jen, Debendra Das Sharma, Bruce Tennant, Prahladachar Jayaprakash Bharadwaj
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Patent number: 11231905Abstract: Various systems and methods for implementing a vehicle with an external speaker and microphone are described herein. A system includes an audio processor to receive audio data, the audio data sensed by a microphone array installed on the vehicle, the audio data generated by a source outside of the vehicle; an audio classification circuit to analyze the audio data using a machine learning technique to determine a sound event; and a vehicle interface to transmit a message to a vehicle control system, the message based on the sound event.Type: GrantFiled: March 27, 2019Date of Patent: January 25, 2022Assignee: Intel CorporationInventors: Hector Alfonso Cordourier Maruri, Sandra Coello Chavarin, Diego Mauricio Cortés Hernández, Rosa Jacqueline Sanchez Mesa, Lizbeth De la Mora Hernandez, Miquel Tlaxcalteco Matus
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Patent number: 11233536Abstract: A wireless communication device can include an antenna array configured to receive a plurality of radio frequency (RF) signals, RF circuitry, and digital baseband receive circuitry. The RF circuitry is configured to process the plurality of RF signals received via the antenna array to generate a single RF signal. The digital baseband receive circuitry is coupled to the RF circuitry and is configured to generate a downconverted signal based on the single RF signal, amplify the downconverted signal to generate an amplified downconverted signal, and convert the amplified downconverted signal to generate a digital output signal for processing by a wireless modem. The digital baseband receive circuitry further includes at least a first filtering system configured to filter the downconverted signal prior to amplification.Type: GrantFiled: March 28, 2018Date of Patent: January 25, 2022Assignee: Intel CorporationInventors: Mohammed Alam, Yiwen Chen, Ricardo Fernandez, John J. Parkes, Jr., James Riches, Werner Schelmbauer, Daniel Schwartz, Michael David Vicker, Dong-Jun Yang
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Patent number: 11231927Abstract: In one embodiment, an apparatus includes: an accelerator to execute instructions; an accelerator request decoder coupled to the accelerator to perform a first level decode of requests from the accelerator and direct the requests based on the first level decode, the accelerator request decoder including a memory map to identify a first address range associated with a local memory and a second address range associated with a system memory; and a non-coherent request router coupled to the accelerator request decoder to receive non-coherent requests from the accelerator request decoder and perform a second level decode of the non-coherent requests, the non-coherent request router to route first non-coherent requests to a sideband router of the first die and to direct second non-coherent requests to a computing die. Other embodiments are described and claimed.Type: GrantFiled: March 8, 2018Date of Patent: January 25, 2022Assignee: Intel CorporationInventors: Lakshminarayana Pappu, Robert D. Adler, Amit Kumar Srivastava, Aravindh Anantaraman