Patents Assigned to Intel Corporations
  • Patent number: 11234269
    Abstract: Methods, computer readable media, and wireless apparatuses are disclosed for virtual carrier sensing with two network allocation vectors (NAV). An apparatus of a wireless device is disclosed. The apparatus comprising processing circuitry configured to: determine a duration of a frame, determine whether the frame is an intra basic service set (Intra-BSS) frame, an inter-BSS frame, or an unclassified frame. The processing circuitry may be further configured to set an intra-BSS network allocation vector (NAV) to the duration of the frame, if the frame is determined to be the intra-BSS frame, and if a receiver address is decoded from the frame and the receiver address is not an address of the wireless device. The processing circuitry may be further configured to set a regular NAV to the duration of the frame, if the frame is determined to be the inter BSS frame or the unclassified frame.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: January 25, 2022
    Assignee: Intel Corporation
    Inventors: Po-Kai Huang, Qinghua Li, Robert J. Stacey
  • Publication number: 20220020716
    Abstract: Embodiments include a mixed hybrid bonding structure comprising a composite dielectric layer, where the composite dielectric layer comprises an organic dielectric material having a plurality of inorganic filler material. One or more conductive substrate interconnect structures are within the composite dielectric layer. A die is on the composite dielectric layer, the die having one or more conductive die interconnect structures within a die dielectric material. The one or more conductive die interconnect structures are directly bonded to the one or more conductive substrate interconnect structures, and the inorganic filler material of the composite dielectric layer is bonded to the die dielectric material.
    Type: Application
    Filed: September 28, 2021
    Publication date: January 20, 2022
    Applicant: Intel Corporation
    Inventors: Shawna Liff, Adel Elsherbini, Johanna Swan, Nagatoshi Tsunoda, Jimin Yao
  • Publication number: 20220020613
    Abstract: Stacked thermal process chamber module for remote radiative heating of semiconductor device workpieces. A stacked thermal process module may include a stack of thermal process chambers and one or more generators of electromagnetic radiation. The electromagnetic radiation may be transported from a generator remote from the process chambers through one or more waveguides, thereby minimizing the volume and/or cleanroom footprint of the stacked thermal process chamber module. A waveguide may terminate in a process chamber so that electromagnetic radiation delivered during a thermal process may be coupled into one or more materials of the workpiece. The radiative heating process may overcome many of the limitations of thermal process chambers that instead employ a local heat source located within a process chamber.
    Type: Application
    Filed: July 17, 2020
    Publication date: January 20, 2022
    Applicant: Intel Corporation
    Inventors: Ashutosh Sagar, Chao-Kai Liang, Miye Hopkins, Weimin Han, Robert James
  • Publication number: 20220021475
    Abstract: Mixed mode constellation mapping to map a data block to a block of sub-carriers based on a configurable set of one or more constellation mapping schemes, and corresponding mixed mode least likelihood ratio (LLR) de-mapping based on the configurable set of one or more modulation schemes. The set may be configurable to include multiple modulation schemes to provide to a SEvSNR measure that is a non-weighted or weighted average of SEvSNR measures of the multiple modulation schemes. Mixed mode constellation mapping may be useful be configurable to control spectral efficiency versus SNR (SEvSNR) over a range of SNR with relatively fine SNR granularity, and may be configurable to control SEvSNR over a range of SNR at a fixed FEC code rate, which may include a highest available or highest permitted code rate.
    Type: Application
    Filed: July 23, 2021
    Publication date: January 20, 2022
    Applicant: Intel Corporation
    Inventors: Bernard Arambepola, Noam Tal, Sahan S. Gamage, Thushara Hewavithana, Shaul Shulman
  • Publication number: 20220021517
    Abstract: Technologies for secure data transfer of MMIO data between a processor and an accelerator. A MIMO security engine includes a first block cipher pipeline to encrypt a count using a key; a first exclusive-OR (XOR) to generate a first XOR result of the encrypted count and a length multiplied by an authentication key; a second block cipher pipeline to encrypt (count+1) using the key; a second XOR to generate a second XOR result of plaintext data and the encrypted (count+1); a plurality of Galois field multipliers (GFMs) to perform Galois field multiplication on additional authenticated data (AAD), powers of the authentication key, and ciphertext data; and a plurality of exclusive-ORs (XORs) to combine results of the GFMs and the first XOR result to generate an authentication tag. Other embodiments are described and claimed.
    Type: Application
    Filed: June 8, 2021
    Publication date: January 20, 2022
    Applicant: Intel Corporation
    Inventors: Santosh Ghosh, Luis Kida, Reshma Lal
  • Publication number: 20220019432
    Abstract: A processor includes an execution unit and a processing logic operatively coupled to the execution unit, the processing logic to: enter a first execution state and transition to a second execution state responsive to executing a control transfer instruction. Responsive to executing a target instruction of the control transfer instruction, the processing logic further transitions to the first execution state responsive to the target instruction being a control transfer termination instruction of a mode identical to a mode of the processing logic following the execution of the control transfer instruction; and raises an execution exception responsive to the target instruction being a control transfer termination instruction of a mode different than the mode of the processing logic following the execution of the control transfer instruction.
    Type: Application
    Filed: August 17, 2021
    Publication date: January 20, 2022
    Applicant: Intel Corporation
    Inventors: Vedvyas Shanbhogue, Jason W. Brandt, Ravi L. Sahita, Xiaoning Li
  • Publication number: 20220020156
    Abstract: An embodiment of an image processing apparatus may comprise one or more processors, memory coupled to the one or more processor to store image and mask data, and logic coupled to the one or more processors and the memory, the logic to capture a volumetric broadcast video signal in real-time and generate a sequence of frame images from the captured real-time volumetric broadcast video signal, segment an input image, which corresponds to a single frame of the sequence of frame images, to generate a mask image associated with the input image, and determine a mask quality score based on the input image and the associated mask image in real-time. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: September 29, 2021
    Publication date: January 20, 2022
    Applicant: Intel Corporation
    Inventors: Fahim Mohammad, Joseph Batz, Nathan Segerlind, Itay Benou, Tzachi Hershkovich
  • Publication number: 20220019431
    Abstract: A processing apparatus is provided comprising a multiprocessor having a multithreaded architecture. The multiprocessor can execute at least one single instruction to perform parallel mixed precision matrix operations. In one embodiment the apparatus includes a memory interface and an array of multiprocessors coupled to the memory interface. At least one multiprocessor in the array of multiprocessors is configured to execute a fused multiply-add instruction in parallel across multiple threads.
    Type: Application
    Filed: July 6, 2021
    Publication date: January 20, 2022
    Applicant: Intel Corporation
    Inventors: Himanshu Kaul, Mark A. Anders, Sanu K. Mathew, Anbang Yao, Joydeep Ray, Ping T. Tang, Michael S. Strickland, Xiaoming Chen, Tatiana Shpeisman, Abhishek R. Appu, Altug Koker, Kamal Sinha, Balaji Vembu, Nicolas C. Galoppo Von Borries, Eriko Nurvitadhi, Rajkishore Barik, Tsung-Han Lin, Vasanth Ranganathan, Sanjeev Jahagirdar
  • Publication number: 20220021546
    Abstract: The disclosed embodiments enable applying production nature to a software signature post-build (or even post-release), where the signature type is determined by the existence of a production-signed intermediate CA certificate—either hosted in the cloud (for pure release immutability), or re-ingested into the package (if certain modification are allowed). This allows a so-called deferred issuance of the product release. Even if the CA certificate is to be reinserted into the package, this modification likely affects only the delivery shell (e.g., installer) and may not require format-specific binary changes of, possibly heterogeneous, artifacts therein.
    Type: Application
    Filed: June 25, 2021
    Publication date: January 20, 2022
    Applicant: Intel Corporation
    Inventor: Mateusz Bronk
  • Publication number: 20220019098
    Abstract: An optical modulator includes a substrate, a first dielectric layer over the substrate, a rib waveguide including a PN junction on the first dielectric, a second dielectric layer over the rib waveguide and a stressor layer including a metal, where the first or the second dielectric is between the stressor layer and the PN junction.
    Type: Application
    Filed: December 22, 2020
    Publication date: January 20, 2022
    Applicant: Intel Corporation
    Inventors: Mengyuan Huang, David Patel, Kejia Li, Wei Qian, Ansheng Liu
  • Publication number: 20220021917
    Abstract: In one embodiment, an edge compute node comprises processing circuitry to: receive an incoming video stream captured by a camera, wherein the incoming video stream comprises a plurality of video segments; store the plurality of video segments in a receive buffer in a memory; perform a visual computing task on a first video segment in the receive buffer; detect a resource overload on the edge compute node; receive load information corresponding to a plurality of peer compute nodes; select a peer compute node to perform the visual computing task on a second video segment in the receive buffer; replicate the second video segment from the edge compute node to the peer compute node; and receive a compute result from the peer compute node, wherein the compute result is based on the peer compute node performing the visual computing task on the second video segment.
    Type: Application
    Filed: April 2, 2021
    Publication date: January 20, 2022
    Applicant: Intel Corporation
    Inventors: Yi Zou, Mohammad Ataur Rahman Chowdhury
  • Publication number: 20220021583
    Abstract: A gateway is provided with configuration management logic to identify a set of configurations corresponding to a deployment of a particular application, and automatically send corresponding configuration data to a set of devices in range of the gateway. Service management logic of the gateway determines that assets on the set of devices correspond to one or more asset abstractions defined for the particular application, where the configuration data is sent to the set of devices based on the assets corresponding to the asset abstractions. Sensor data is received during the deployment as generated by a sensor asset of one of the devices, the sensor data is processed according to service logic of the particular application to generate a result, and actuating data is generated and sent during the deployment to an actuator asset on the set of devices based on the result.
    Type: Application
    Filed: May 3, 2021
    Publication date: January 20, 2022
    Applicant: Intel Corporation
    Inventors: Silviu Petria, Andra Paraschiv, George Cristian Dumitru Milescu, Ulf Christian Bjorkengren, Shao-Wen Yang
  • Publication number: 20220021906
    Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.
    Type: Application
    Filed: September 28, 2021
    Publication date: January 20, 2022
    Applicant: INTEL CORPORATION
    Inventors: Jorge E. Caviedes, Mahesh M. Subedar, Khasim S. Dudekula
  • Publication number: 20220019667
    Abstract: In one embodiment, an apparatus comprises a processor to: receive a request to configure a secure execution environment for a first workload; configure a first set of secure execution enclaves for execution of the first workload, wherein the first set of secure execution enclaves is configured on a first set of processing resources, wherein the first set of processing resources comprises one or more central processing units and one or more accelerators; configure a first set of secure datapaths for communication among the first set of secure execution enclaves during execution of the first workload, wherein the first set of secure datapaths is configured over a first set of interconnect resources; configure the secure execution environment for the first workload, wherein the secure execution environment comprises the first set of secure execution enclaves and the first set of secure datapaths.
    Type: Application
    Filed: June 22, 2021
    Publication date: January 20, 2022
    Applicant: Intel Corporation
    Inventors: Kapil Sood, Ioannis T. Schoinas, Yu-Yuan Chen, Raghunandan Makaram, David J. Harriman, Baiju Patel, Ronald Perez, Matthew E. Hoekstra, Reshma Lal
  • Patent number: 11226660
    Abstract: A multiple mode display apparatus and methods of use. An apparatus includes a display surface with a first and a second display area. A housing pivotally attached with the display proximate a first edge of the housing is displaceable from a coplanar position with the surface of the display device to a position wherein an angle of at least 90 degrees between the surface of the display and the housing is formed along said first edge. In the first position, the first display area is visible and activated to receive user input or to display output. The second display area is covered by the housing and placed in a mode of reduced power consumption. In the second position, the second display area is visible and activated to display output.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: January 18, 2022
    Assignee: Intel Corporation
    Inventor: Nicholas W. Oakley
  • Patent number: 11229052
    Abstract: Methods and systems herein provide better downlink (DL) data throughput for cell-edge stations (CE STAs). The systems enable protection from a third-party collision during a wideband DL data transmission to the cell edge STA, when the wideband control frame, such as clear-to-send (CTS) or acknowledge (ACK), transmission from a cell edge STA cannot reach the AP. This process can be achieved by designing a new wideband control frame comprising: a legacy preamble sent over the primary 20 MHz channel that can be decoded by the legacy STAs, a new preamble sent over the primary 20 MHz channel that can be used to identify the new wideband control frame (this new preamble has the total signal bandwidth information for the rest of the packet following the new preamble); and duplicate legacy control packets set over the total bandwidth indicated in the new preamble (the legacy control packets can be decoded by the legacy STAs).
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: January 18, 2022
    Assignee: Intel Corporation
    Inventors: Juan Fang, Minyoung Park, Shahrnaz Azizi
  • Patent number: 11226353
    Abstract: An electrical characterization and fault isolation probe can include a cable, a connector, and a coating over a portion of the cable. The cable can have a first conductor having a first impedance, a second conductor having a second impedance, and a dielectric surrounding the first conductor and electrically isolating the first conductor from the second conductor. The connector can physically couple to, and be in electrical communication with, the cable. The connector can include a first electrical communication pathway and a second electrical communication pathway. The first electrical communication pathway can be electrically isolated from the second electrical communication pathway. The first electrical communication pathway can be in electrical communication with the first conductor. The second electrical communication pathway can be in electrical communication with the second conductor. The connector can have a fifth impedance.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: January 18, 2022
    Assignee: Intel Corporation
    Inventors: Chengqing Hu, Mayue Xie, Simranjit S. Khalsa, Deepak Goyal
  • Patent number: 11227766
    Abstract: A dielectric composition including a metal oxide particle including a diameter of 5 nanometers or less capped with an organic ligand at at least a 1:1 ratio. A method including synthesizing metal oxide particles including a diameter of 5 nanometers or less; and capping the metal oxide particles with an organic ligand at at least a 1:1 ratio. A method including forming an interconnect layer on a semiconductor substrate; forming a first hardmask material and a different second hardmask material on the interconnect layer, wherein at least one of the first hardmask material and the second hardmask material is formed over an area of interconnect layer target for a via landing and at least one of the first hardmask material and the second hardmask material include metal oxide nanoparticles; and forming an opening to the interconnect layer selectively through one of the first hardmask material and the second hardmask material.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: January 18, 2022
    Assignee: Intel Corporation
    Inventors: Marie Krysak, Florian Gstrein, Manish Chandhok
  • Patent number: 11228539
    Abstract: Technologies for network interface controllers (NICs) include a compute sled and an accelerator sled in communication over a network. The accelerator sled configures a virtual switch endpoint associated with a remote direct memory access (RDMA) server instance that is associated with a field-programmable gate array (FPGA) of the accelerator sled. The accelerator sled updates local software defined networking (SDN) tables with a virtual tunnel associated with the virtual switch endpoint and a remote compute sled. A virtual switch of the accelerator sled switches virtual tunnel traffic from the remote compute sled to the RDMA server instance, which transfers data to or from the FPGA. The compute sled also updates a local SDN table with the virtual tunnel, and a virtual switch of the compute sled switches virtual tunnel traffic to or from the accelerator sled. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: January 18, 2022
    Assignee: Intel Corporation
    Inventors: Mrittika Ganguli, Sugesh Chandran, Parthasarathy Sarangam, Sujoy Sen, Susanne M. Balle, Rajesh Sankaran
  • Patent number: 11226653
    Abstract: Various systems and methods for managing an ambient user interface on a laptop are described herein. A laptop device includes an upper portion including a display device and a lower portion coupled to the upper portion with a hinge mechanism, the lower portion including a reflective surface. When the laptop device is closed and the upper portion abuts the lower portion, the display device is configured to display images that are reflected on the reflective surface.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: January 18, 2022
    Assignee: Intel Corporation
    Inventors: Shantanu Dattatraya Kulkarni, Tongyan Zhai, Prosenjit Ghosh