Patents Assigned to Intel Corporations
-
Publication number: 20220011869Abstract: Particular embodiments described herein provide for an electronic device that can be configured to include a virtual reality engine to create a virtual environment for a user, a communication engine in communication with at least one reference point pad on the user, and a haptic actuator location engine to determine a position of one or more removable haptic pads on the user using sensor data from the one or more removable haptic pads and the at least one reference point pad. In an example, the sensor data is motion data from an accelerometer, gyroscope, or some other sensor(s) to detect movement of the one or more removable haptic pads and the at least one reference point pad.Type: ApplicationFiled: September 23, 2021Publication date: January 13, 2022Applicant: Intel CorporationInventor: Sean Jude William Lawrence
-
Publication number: 20220014363Abstract: Combined post-quantum security utilizing redefined polynomial calculation is described. An example of an apparatus includes a first circuit for key encapsulation operation; a second circuit for digital signature operation; and a NTT (Number Theoretic Transform) multiplier circuit, wherein the NTT multiplier circuit provides for polynomial multiplication for both the first circuit and the second circuit, wherein the apparatus is to remap coefficients of polynomials for the first circuit to a prime modulus for the second circuit, and perform polynomial multiplication for the first circuit utilizing the remapped coefficients of the polynomials for the first circuit.Type: ApplicationFiled: September 24, 2021Publication date: January 13, 2022Applicant: Intel CorporationInventors: Andrea Basso, Santosh Ghosh, Manoj Sastry
-
Publication number: 20220012188Abstract: Technologies disclosed herein provide one example of a system that includes processor circuitry and integrity circuitry. The processor circuitry is to receive a first request associated with an application to perform a memory access operation for an address range in a memory allocation of memory circuitry. The integrity circuitry is to determine a location of a metadata region within a cacheline that includes at least some of the address range, identify a first portion of the cacheline based at least in part on a first data bounds value stored in the metadata region, generate a first integrity value based on the first portion of the cacheline, and prevent the memory access operation in response to determining that the first integrity value does not correspond to a second integrity value stored in the metadata region.Type: ApplicationFiled: September 24, 2021Publication date: January 13, 2022Applicant: Intel CorporationInventors: David M. Durham, Michael LeMay, Santosh Ghosh, Sergej Deutsch
-
Publication number: 20220012189Abstract: A shared memory controller is to service load and store operations received, over data links, from a plurality of independent nodes to provide access to a shared memory resource. Each of the plurality of independent nodes is to be permitted to access a respective portion of the shared memory resource. Interconnect protocol data and memory access protocol data are sent on the data links and transitions between the interconnect protocol data and memory access protocol data can be defined and identified.Type: ApplicationFiled: September 25, 2021Publication date: January 13, 2022Applicant: Intel CorporationInventors: Debendra Das Sharma, Robert G. Blankenship, Suresh S. Chittor, Kenneth C. Creta, Balint Fleischer, Michelle C. Jen, Mohan J. Kumar, Brian S. Morris
-
Publication number: 20220012203Abstract: Systems, methods, and devices can involve a host device that includes a root complex, a link, and an interconnect protocol stack coupled to a bus link. The interconnect protocol stack can include multiplexing logic to select one of a Peripheral Component Interconnect Express (PCIe) upper layer mode, or an accelerator link protocol upper layer mode, the PCIe upper layer mode or the accelerator link protocol upper layer mode to communicate over the link, and physical layer logic to determine one or more low latency features associated with one or both of the PCIe upper layer mode or the accelerator link protocol upper layer mode.Type: ApplicationFiled: September 25, 2021Publication date: January 13, 2022Applicant: Intel CorporationInventors: Debendra Das Sharma, Michelle C. Jen, Prahladachar Jayaprakash Bharadwaj, Bruce A. Tennant, Mahesh Wagh
-
Patent number: 11222082Abstract: Particular embodiments described herein provide for a system that can be configured to determine an identification (ID) of a computer processing unit (CPU) using one or more tests and/or measurements, intercept the result of a query from a process to determine the ID of the CPU, replace the result of the query if the result of the query does not match the determined ID of the CPU, and communicate the result of the query that includes the determined ID of the CPU to the process. In an example, the query is a CPUID opcode and the results of the query are intercepted after passing through a hypervisor.Type: GrantFiled: March 30, 2018Date of Patent: January 11, 2022Assignee: Intel CorporationInventor: Alexander Komarov
-
Patent number: 11222545Abstract: Technologies for providing signal quality based route management for unmanned aerial vehicles include a device that includes circuitry to produce a data set indicative of a wireless communication signal quality at each of multiple locations in a geographic area. The circuitry is also to produce, as a function of the data set and a target wireless communication signal quality, a planned route for a vehicle through the geographic area.Type: GrantFiled: June 28, 2019Date of Patent: January 11, 2022Assignee: Intel CorporationInventors: Shu-Ping Yeh, Jingwen Bai, Feng Xue, Mark Davis, Shilpa Talwar
-
Patent number: 11223831Abstract: Techniques related to video coding using content based metadata.Type: GrantFiled: August 6, 2019Date of Patent: January 11, 2022Assignee: Intel CorporationInventors: Frederic J. Noraz, Jill M. Boyce, Sumit Mohan
-
Patent number: 11222836Abstract: Device package and a method of forming a device package are described. The device package includes an interposer with interconnects on an interconnect package layer and a conductive layer on the interposer. The device package has dies on the conductive layer, where the package layer includes a zero-misalignment two-via stack (ZM2VS) and a dielectric. The ZM2VS directly coupled to the interconnect. The ZM2VS further includes the dielectric on a conductive pad, a first via on a first seed, and first seed on a top surface of the conductive pad, where the first via extends through dielectric. The ZM2VS also has a conductive trace on dielectric, and a second via on a second seed, the second seed is on the dielectric, where the conductive trace connects to first and second vias, where second via connects to an edge of conductive trace opposite from first via.Type: GrantFiled: December 30, 2017Date of Patent: January 11, 2022Assignee: Intel CorporationInventors: Veronica Strong, Aleksandar Aleksov, Brandon Rawlings, Johanna Swan
-
Patent number: 11223879Abstract: Providing adaptive visual browsing of digital content may be accomplished by presenting a scrolling ticker on a display for browsing of digital content available for viewing by a user of a processing system, the ticker having a plurality of items, each item including an image representing at least one of a content title and a content service provider; receiving a user input selection from a remote control device operated by the user, the user input selection selecting one of the ticker items to indicate the user's interest in the selected item; and changing at least one of the items in the ticker to another item in response to the user input selection, wherein the other item has metatags similar to or related to metatags of the selected item.Type: GrantFiled: April 20, 2020Date of Patent: January 11, 2022Assignee: Intel CorporationInventors: Sean Dunnahoo, Christie Flynn
-
Patent number: 11222977Abstract: Integrated circuit transistor structures are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent shallow trench isolation (STI) regions during fabrication. The n-MOS transistor device may include at least 75% germanium by atomic percentage. In an example embodiment, the structure includes an intervening diffusion barrier deposited between the n-MOS transistor and the STI region to provide dopant diffusion reduction. In some embodiments, the diffusion barrier may include silicon dioxide with carbon concentrations between 5 and 50% by atomic percentage. In some embodiments, the diffusion barrier may be deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) techniques to achieve a diffusion barrier thickness in the range of 1 to 5 nanometers.Type: GrantFiled: September 26, 2017Date of Patent: January 11, 2022Assignee: Intel CorporationInventors: Glenn A. Glass, Anand S. Murthy, Karthik Jambunathan, Cory C. Bomberger, Tahir Ghani, Jack T. Kavalieros, Benjamin Chu-Kung, Seung Hoon Sung, Siddharth Chouksey
-
Patent number: 11221849Abstract: Disclosed embodiments relate to executing a vector multiplication instruction. In one example, a processor includes fetch circuitry to fetch the vector multiplication instruction having fields for an opcode, first and second source identifiers, and a destination identifier, decode circuitry to decode the fetched instruction, execution circuitry to, on each of a plurality of corresponding pairs of fixed-sized elements of the identified first and second sources, execute the decoded instruction to generate a double-sized product of each pair of fixed-sized elements, the double-sized product being represented by at least twice a number of bits of the fixed size, and generate an unsigned fixed-sized result by rounding the most significant fixed-sized portion of the double-sized product to fit into the identified destination.Type: GrantFiled: September 27, 2017Date of Patent: January 11, 2022Assignee: Intel CorporationInventors: Venkateswara R. Madduri, Carl Murray, Elmoustapha Ould-Ahmed-Vall, Mark J. Charney, Robert Valentine, Jesus Corbal
-
Patent number: 11222921Abstract: Disclosed herein are selector devices and related devices and techniques. In some embodiments, a selector device may include a first electrode, a second electrode, and a selector material between the first electrode and the second electrode. The selector material may include a dielectric material and a conductive dopant.Type: GrantFiled: August 29, 2017Date of Patent: January 11, 2022Assignee: Intel CorporationInventors: Abhishek A. Sharma, Ravi Pillarisetty, Van H. Le, Gilbert W. Dewey, Willy Rachmady
-
Patent number: 11222987Abstract: In embodiments, an optoelectronic apparatus may include a substrate with a first side and a second side opposite the first side; a photodetector disposed on the first side of the substrate, the photodetector to convert a light signal into an electrical signal; and a dielectric metasurface lens etched into the second side of the substrate, the dielectric metasurface lens to collect incident light and focus it through the substrate onto the photodetector.Type: GrantFiled: March 21, 2018Date of Patent: January 11, 2022Assignee: Intel CorporationInventors: John Heck, Harel Frish, Paul R. West
-
Patent number: 11221857Abstract: The present invention relates to a platform power management scheme. In some embodiments, a platform provides a relative performance scale using one or more parameters to be requested by an OSPM system.Type: GrantFiled: April 18, 2019Date of Patent: January 11, 2022Assignee: Intel CorporationInventors: Guy M. Therien, Paul S. Diefenbaugh, Anil Aggarwal, Andrew D. Henroid, Jeremy J. Shrall, Efraim Rotem, Krishnakanth V. Sistla, Eliezer Weissmann
-
Patent number: 11222462Abstract: A method for improving performance of generation of digitally represented graphics. The method comprises: receiving a first representation of a base primitive; providing a set of instructions associated with vertex position determination; executing said retrieved set of instructions on said first representation of said base primitive using bounded arithmetic for providing a second representation of said base primitive, and subjecting said second representation of said base primitive to a culling process. A corresponding apparatus and computer program product are also presented.Type: GrantFiled: January 15, 2019Date of Patent: January 11, 2022Assignee: Intel CorporationInventors: Jon N. Hasselgren, Jacob J. Munkberg, Franz Petrik Clarberg, Tomas G. Akenine-Moller
-
Patent number: 11221687Abstract: One embodiment provides a method. The method includes receiving, with a computing system, stylus orientation data representing an orientation of a stylus. The method includes receiving, with a computing system, grip characteristics data representing a grip on the stylus by a user. The method includes identifying, with the computing system, a stylus mode for use by the computing system, at least partially based on the stylus orientation data and the grip characteristics data. The method includes applying the stylus mode to the computing system to interpret interaction data representing interactions of the stylus with the computing system.Type: GrantFiled: May 11, 2020Date of Patent: January 11, 2022Assignee: Intel CorporationInventors: Arvind Kumar, Amy Wiles
-
Patent number: 11221848Abstract: Embodiments described herein provide an apparatus comprising a plurality of processing resources including a first processing resource and a second processing resource, a shared local memory communicatively coupled to the first processing resource and the second processing resource, and a processor to receive an instruction to initiate a matrix multiplication operation, write a first set of matrix data into a first set of registers, and share the first set of matrix data between the first processing resource and the second processing resource for use in the matrix multiplication operation. Other embodiments may be described and claimed.Type: GrantFiled: September 25, 2019Date of Patent: January 11, 2022Assignee: INTEL CORPORATIONInventors: Subramaniam Maiyuran, Varghese George, Joydeep Ray, Ashutosh Garg, Jorge Parra, Shubh Shah, Shubra Marwaha
-
Patent number: 11222877Abstract: The present disclosure is directed to systems and methods for improving heat distribution and heat removal efficiency in PoP semiconductor packages. A PoP semiconductor package includes a first semiconductor package that is physically, communicably, and conductively coupled to a stacked second semiconductor package. A thermally conductive member that includes at least one thermally conductive member may be disposed between the first semiconductor package and the second semiconductor package. The thermally conductive member may include: a single thermally conductive element; multiple thermally conductive elements; or a core that includes at least one thermally conductive element. The thermally conductive elements are thermally conductively coupled to an upper surface of the first semiconductor package and to the lower surface of the second semiconductor package to facilitate the transfer of heat from the first semiconductor package to the second semiconductor package.Type: GrantFiled: September 29, 2017Date of Patent: January 11, 2022Assignee: Intel CorporationInventors: Omkar Karhade, Robert L. Sankman, Nitin A. Deshpande, Mitul Modi, Thomas J. De Bonis, Robert M. Nickerson, Zhimin Wan, Haifa Hariri, Sri Chaitra J. Chavali, Nazmiye Acikgoz Akbay, Fadi Y. Hafez, Christopher L. Rumer
-
Patent number: 11223882Abstract: Techniques for acoustic management of entertainment devices and systems are described. Various embodiments may include techniques for acoustically determining a location of a remote control or other entertainment device. Some embodiments may include techniques for controlling one or more entertainment components using voice commands or other acoustic information. Other embodiments may include techniques for establishing a voice connection using a remote control device. Other embodiments are described and claimed.Type: GrantFiled: April 13, 2020Date of Patent: January 11, 2022Assignee: INTEL CORPORATIONInventors: Bran Ferren, Cory J. Booth, David B. Andersen