Patents Assigned to Intel Corporations
  • Publication number: 20240406380
    Abstract: A block of a video frame can be encoded using inter-prediction, and the motion vector of the block can be encoded based on a motion vector reference of a merge candidate. Some video codecs allow a large range of temporal and spatial neighbors to be considered as potential merge candidates. It is not practical to perform motion compensation and rate-distortion optimization for all possible merge candidates. To address this concern, a hardware-efficient process can be implemented to rank and select merge candidates. A reference frame priority list is applied to select a subset of potential reference frame combinations. An efficient top-K sorting algorithm is applied to identify merge candidates for each reference frame combination and keep top merge candidates with highest weights. Motion compensation and rate-distortion optimization are performed on the top merge candidates only.
    Type: Application
    Filed: August 8, 2024
    Publication date: December 5, 2024
    Applicant: Intel Corporation
    Inventors: Qian Xu, Jian Hu, Navyasree Matturu, Dmitry E. Ryzhov, Satya N. Yedidi
  • Publication number: 20240403376
    Abstract: Embodiments are provided for summarization and recommendation of content. In disclosed embodiments, a summarization engine scores constituent parts of content, and generates a plurality of summaries from a plurality of points of view for the content based at least in part on the scores of constituent parts. The summaries may be formed with constituent parts extracted from the contents. A recommendation engine provides recommendations to a user based on rankings of the summaries generated by the summarization engine. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: August 9, 2024
    Publication date: December 5, 2024
    Applicant: Intel Corporation
    Inventors: Nirmit Parikh, Tanmay Hiren Desai
  • Publication number: 20240405433
    Abstract: Disclosed herein are antenna modules, electronic assemblies, and communication devices. An example antenna module includes an IC component, an antenna patch support over a face of the IC component, and a stack of antenna patches vertically arranged at least partially above one another, where a first antenna patch of the stack is an antenna patch closest to the IC component, and a second antenna patch of the stack is an antenna patch closest to the first antenna patch. The first antenna patch is on the face of the IC component while the second and further antenna patches of the stack are on or in the antenna patch support and are electrically isolated from all electrically conductive material pathways in the antenna patch support and in the IC component.
    Type: Application
    Filed: June 2, 2023
    Publication date: December 5, 2024
    Applicant: Intel Corporation
    Inventors: Telesphor Kamgaing, Georg Seidemann, Harald Gossner, Thomas Wagner, Bernd Waidhas, Tae Young Yang
  • Publication number: 20240404917
    Abstract: Devices, transistor structures, systems, and techniques are described herein related to coupling backside and frontside metallization layers that are on opposite sides of a device layer. A device includes a transistor having semiconductor structures extending between a source and a drain, and a gate between the source and drain, a bridge via extending between a frontside metallization over the transistor and a backside metallization below the transistor, and a thin insulative liner between the bridge via and components of the transistor.
    Type: Application
    Filed: June 1, 2023
    Publication date: December 5, 2024
    Applicant: Intel Corporation
    Inventors: Sikandar Abbas, Chanaka Munasinghe, Leonard Guler, Reza Bayati, Madeleine Stolt, Makram Abd El Qader, Pratik Patel, Anindya Dasgupta
  • Publication number: 20240407092
    Abstract: Covers for integrated circuit package sockets are disclosed herein. An example cover for a socket for an integrated circuit package includes a base including a cutout, the cutout to engage a pin associated with the socket, engagement of the cutout and the pin to maintain a position of the cover relative to the socket; and a handle to facilitate positioning of the cover to move the cutout into engagement with the pin.
    Type: Application
    Filed: August 15, 2024
    Publication date: December 5, 2024
    Applicant: Intel Corporation
    Inventors: Ariatne Ramirez Macias, Allison Van Horn, Kristin L. Weldon, Israel Cruz Ruiz, Fernando Gonzalez Lenero, Min Pei, Francisco Javier Colorado Alonso, Randall Scott Sanford, Emery Evon Frey, Eric W. Buddrius
  • Publication number: 20240402443
    Abstract: A kinematically aligned optical connector may be implemented with a silicon PIC component and a glass substrate component. The kinematically aligned optical connector includes one or more kinematic connectors or mechanical alignment features and visual fiducials that enable true kinematic coupling (i.e., in a three-dimensional Cartesian coordinate system, full constraint in all 6 degrees of freedom, meaning, X, Y, Z planes and all 3 angles), and enables an increased thickness of the glass substrate material of the glass waveguide substrate.
    Type: Application
    Filed: May 30, 2023
    Publication date: December 5, 2024
    Applicant: Intel Corporation
    Inventors: John M. Heck, Saeed Fathololoumi, Harel Frish, Sang Yup Kim, Hari Mahalingam, Nicholas D. Psaila
  • Publication number: 20240403620
    Abstract: An apparatus to facilitate acceleration of machine learning operations is disclosed. The apparatus comprises at least one processor to perform operations to implement a neural network and accelerator logic to perform communicatively coupled to the processor to perform compute operations for the neural network.
    Type: Application
    Filed: May 31, 2024
    Publication date: December 5, 2024
    Applicant: Intel Corporation
    Inventors: Amit Bleiweiss, Anavai Ramesh, Asit Mishra, Deborah Marr, Jeffrey Cook, Srinivas Sridharan, Eriko Nurvitadhi, Elmoustapha Ould-Ahmed-Vall, Dheevatsa Mudigere, Mohammad Ashraf Bhuiyan, Md Faijul Amin, Wei Wang, Dhawal Srivastava, Niharika Maheshwari
  • Publication number: 20240402442
    Abstract: The substrate of an integrated circuit component comprises a cutout that extends fully or partially through the substrate. An edge of a photonic integrated circuit (PIC) in the integrated circuit component is coplanar with a wall of the cutout or extends into the cutout. An optical fiber in an FAU is aligned with a waveguide within the PIC and the FAU is attached to the PIC edge and an attachment block. The attachment block provides an increased attachment surface area for the FAU. A portion of the FAU extends into the substrate cutout. A stress relief mechanism can secure the fiber optic cable attached to the FAU to the substrate to at least partially isolate the FAU-PIC attachment from external mechanical forces applied to the optical fiber cable. The integrated circuit component can be attached to a socket that comprises a socket cutout into which an FAU can extend.
    Type: Application
    Filed: May 31, 2023
    Publication date: December 5, 2024
    Applicant: Intel Corporation
    Inventors: Chia-Pin Chiu, Xiaoqian Li, Kaveh Hosseini, Tim T. Hoang
  • Publication number: 20240407142
    Abstract: Hybrid and adaptive cooling systems are described. A method comprises selecting a cooling system type from a set of cooling system types of a hybrid cooling system to cool an electronic component of an electronic device, generating a control directive to activate a cooling component of the cooling system type, and performing thermal management of the electronic component of the electronic device using the cooling component of the cooling system type. Other embodiments are described and claimed.
    Type: Application
    Filed: August 9, 2024
    Publication date: December 5, 2024
    Applicant: INTEL CORPORATION
    Inventors: Francesc Guim Bernat, Karthik Kumar, Uzair Qureshi, Marcos Carranza, Marek Piotrowski
  • Publication number: 20240402828
    Abstract: Gesture input with multiple displays, views, and physics is described. In one example, a method includes generating a three dimensional space having a plurality of objects in different positions relative to a user and a virtual object to be manipulated by the user, presenting, on a display, a displayed area having at least a portion of the plurality of different objects, detecting an air gesture of the user against the virtual object, the virtual object being outside the displayed area, generating a trajectory of the virtual object in the three-dimensional space based on the air gesture, the trajectory including interactions with objects of the plurality of objects in the three-dimensional space, and presenting a portion of the generated trajectory on the displayed area.
    Type: Application
    Filed: June 27, 2024
    Publication date: December 5, 2024
    Applicant: Intel Corporation
    Inventor: Glen J. Anderson
  • Patent number: 12159901
    Abstract: Gate-all-around integrated circuit structures having source or drain structures with epitaxial nubs, and methods of fabricating gate-all-around integrated circuit structures having source or drain structures with epitaxial nubs, are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first pair of epitaxial source or drain structures includes vertically discrete portions aligned with the first vertical arrangement of horizontal nanowires. A second pair of epitaxial source or drain structures includes vertically discrete portions aligned with the second vertical arrangement of horizontal nanowires. A conductive contact structure is laterally between and in contact with the one of the first pair of epitaxial source or drain structures and the one of the second pair of epitaxial source or drain structures.
    Type: Grant
    Filed: November 7, 2022
    Date of Patent: December 3, 2024
    Assignee: Intel Corporation
    Inventors: Cory Bomberger, Anand Murthy, Mark T. Bohr, Tahir Ghani, Biswajeet Guha
  • Patent number: 12159840
    Abstract: Embodiments disclosed herein include multi-die packages with interconnects between the dies. In an embodiment, an electronic package comprises a package substrate, and a first die over the package substrate. In an embodiment, the first die comprises a first IO bump map, where bumps of the first IO bump map have a first pitch. In an embodiment, the electronic package further comprises a second die over the package substrate. In an embodiment, the second die comprises a second IO bump map, where bumps of the second IO bump map have a second pitch that is different than the first pitch. In an embodiment, the electronic package further comprises interconnects between the first IO bump map and the second IO bump map.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: December 3, 2024
    Assignee: Intel Corporation
    Inventors: Zhiguo Qian, Gerald Pasdast, Juan Zeng, Peipei Wang, Ahmad Siddiqui, Lakshmipriya Seshan
  • Patent number: 12160830
    Abstract: This disclosure describes systems, methods, and devices related to initial power state. A device may identify a request frame received from a non-AP MLD on a first link of a plurality of links, wherein the non-AP MLD comprises a plurality of station devices (STAs), and wherein the first link is associated with a first STA of the plurality of STAs. The device may cause to send a response frame to the non-AP MLD on the first link to establish the plurality of links between the device and the non-AP MLD. The device may determine, based on the request frame, a power save mode associated with each of the STAs of the non-AP MLD. The device may communicate with the non-AP MLD based on the power save mode.
    Type: Grant
    Filed: May 18, 2023
    Date of Patent: December 3, 2024
    Assignee: Intel Corporation
    Inventors: Laurent Cariou, Po-Kai Huang, Alexander Min, Minyoung Park
  • Patent number: 12160492
    Abstract: Examples described herein relate to a network interface comprising physical medium dependent (PMD) circuitry, the PMD circuitry to during link training of at least one lane consistent with IEEE 802.3, exit to TIME_OUT state during TRAIN_LOCAL state based on consideration of expiration of a wait timer, loss of local_tf_lock state, and loss of remote_tf_lock state. In some examples, during link training for at least one lane consistent with IEEE 802.3, the PMD circuitry is to exit to TIME_OUT state during TRAIN_REMOTE state based on consideration of expiration of a wait timer, loss of local_tf_lock state, and loss of remote_tf_lock state. In some examples, link training consistent with IEEE 802.3 comprises performance of the PMD control function in Section 162.8.11 of IEEE 802.3ck.
    Type: Grant
    Filed: September 28, 2023
    Date of Patent: December 3, 2024
    Assignee: Intel Corporation
    Inventor: Kent C. Lusted
  • Patent number: 12160862
    Abstract: A generation-Node B (gNB) configured for unlicensed spectrum operation above 52.6 GHz in a fifth-generation new-radio (NR) system (5GS) may encode a parameter (e.g., ssb-PositionsInBurst) for transmission to a UE (e.g., in the SIB1 or UE specific RRC signalling). The parameter may indicate candidate positions of synchronization signal blocks (SSBs) within a discovery reference signal (DRS) measurement timing configuration (DMTC) transmission window within slots of a system frame (SFN). During the DMTC window, the gNB may perform a LBT procedure on an unlicensed carrier of the unlicensed spectrum to determine if the unlicensed carrier is available. When the LBT is successful (i.e., the unlicensed carrier is available), the gNB may encode a discovery reference signal (DRS) for transmission on the unlicensed carrier. The DRS may include one or more of the SSBs transmitted during the candidate positions that fall within the DRS.
    Type: Grant
    Filed: September 29, 2023
    Date of Patent: December 3, 2024
    Assignee: Intel Corporation
    Inventors: Yingyang Li, Gang Xiong, Bishwarup Mondal, Dae Won Lee
  • Patent number: 12158966
    Abstract: Methods and systems that allow a user to see the people or groups who have access to files that are maintained by a plurality of cloud content sharing services. In particular, the user may see what specific party has access to each particular file or directory, regardless of multiple cloud content sharing services involved. Moreover, a user interface and exposed application program interface allows the user to manipulate the permissions, e.g., granting access, to another person or group, to a file or directory. The user interface may also allow the user to terminate access to the file or directory for a person or group. The user's action to change a permission may be effected independently of the particular cloud content sharing service.
    Type: Grant
    Filed: September 29, 2022
    Date of Patent: December 3, 2024
    Assignee: Intel Corporation
    Inventors: Steven J. Birkel, Rita H. Wouhaybi, Timothy Verrall, Mrigank Shekhar
  • Patent number: 12159209
    Abstract: Systems and methods for an accelerated tuning of hyperparameters of a model supported with prior learnings data include assessing subject models associated with a plurality of distinct sources of transfer tuning data, wherein the assessing includes implementing of: [1] a model relatedness assessment for each of a plurality of distinct pairwise subject models, and [2] a model coherence assessment for each of the plurality of distinct pairwise subject models; constructing a plurality of distinct prior mixture models based on the relatedness metric value and the coherence metric value for each of the plurality of distinct pairwise subject models, identifying sources of transfer tuning data based on identifying a distinct prior mixture model having a satisfactory model evidence fraction; and accelerating a tuning of hyperparameters of the target model based on transfer tuning data associated with the distinct prior mixture model having the satisfactory model evidence fraction.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: December 3, 2024
    Assignee: Intel Corporation
    Inventors: Michael McCourt, Ben Hsu, Patrick Hayes, Scott Clark
  • Patent number: 12160368
    Abstract: Examples described herein relate to a device configured to allocate memory resources for packets received by the network interface based on received configuration settings. In some examples, the device is a network interface. Received configuration settings can include one or more of: latency, memory bandwidth, timing of when the content is expected to be accessed, or encryption parameters. In some examples, memory resources include one or more of: a cache, a volatile memory device, a storage device, or persistent memory. In some examples, based on a configuration settings not being available, the network interface is to perform one or more of: dropping a received packet, store the received packet in a buffer that does not meet the configuration settings, or indicate an error. In some examples, configuration settings are conditional where the settings are applied if one or more conditions is met.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: December 3, 2024
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Patrick Connor, Patrick G. Kutch, John J. Browne, Alexander Bachmutsky
  • Patent number: 12160495
    Abstract: Examples described herein relate to a first central processing unit (CPU) node to generate time stamp counter (TSC) values based on a first clock signal and a second CPU node to generate TSC values based on a second clock signal. In some examples, the first CPU node is to determine at least one network timer time stamp based on the TSC values based on the first clock signal and the second CPU node is to determine at least one network timer time stamp based on the TSC values based on the second clock signal. In some examples, determine at least one network timer time stamp based on the TSC values based on the first clock signal is based on (i) a relationship between the first clock signal and a network interface device main timer and (ii) a relationship between a network timer source and the network interface device main timer.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: December 3, 2024
    Assignee: Intel Corporation
    Inventors: Mark Bordogna, Jonathan A. Robinson, Srinivasan S. Iyengar
  • Patent number: 12160844
    Abstract: Methods and apparatus to control usage of frequency bands for wireless communications are disclosed. An example apparatus includes a future location frequency processor to determine a frequency band associated with a future location of a device and an arrival processor to transmit a low power mode interval to the device based on at least one of a time of arrival of the device at the future location or the frequency band associated with the future location.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: December 3, 2024
    Assignee: Intel Corporation
    Inventors: Ravindra Hegde, Manu Iyengar, Greeshma Pisharody, Arokianadhin Edgard, Rashmi Hegde, Biswanath Goswami